void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
{
portENTER_CRITICAL(&dmaworkaround_mux);
dmaworkaround_channels_busy[dmachan-1] = 0;
if (dmaworkaround_waiting_for_chan == dmachan) {
//Reset DMA
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
dmaworkaround_waiting_for_chan = 0;
//Call callback
dmaworkaround_cb(dmaworkaround_cb_arg);
}
portEXIT_CRITICAL(&dmaworkaround_mux);
}
bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg)
{
int otherchan = (dmachan == 1) ? 2 : 1;
bool ret;
portENTER_CRITICAL(&dmaworkaround_mux);
if (dmaworkaround_channels_busy[otherchan-1]) {
//Other channel is busy. Call back when it's done.
dmaworkaround_cb = cb;
dmaworkaround_cb_arg = arg;
dmaworkaround_waiting_for_chan = otherchan;
ret = false;
} else {
//Reset DMA
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
ret = true;
}
portEXIT_CRITICAL(&dmaworkaround_mux);
return ret;
}
/* "inner" restart function for after RTOS, interrupts & anything else on this
* core are already stopped. Stalls other core, resets hardware,
* triggers restart.
*/
void IRAM_ATTR esp_restart_noos()
{
// Disable interrupts
xt_ints_off(0xFFFFFFFF);
// Enable RTC watchdog for 1 second
rtc_wdt_protect_off();
rtc_wdt_disable();
rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_RTC);
rtc_wdt_set_stage(RTC_WDT_STAGE1, RTC_WDT_STAGE_ACTION_RESET_SYSTEM);
rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_200ns);
rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_200ns);
rtc_wdt_set_time(RTC_WDT_STAGE0, 1000);
rtc_wdt_flashboot_mode_enable();
// Reset and stall the other CPU.
// CPU must be reset before stalling, in case it was running a s32c1i
// instruction. This would cause memory pool to be locked by arbiter
// to the stalled CPU, preventing current CPU from accessing this pool.
const uint32_t core_id = xPortGetCoreID();
const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
esp_cpu_reset(other_core_id);
esp_cpu_stall(other_core_id);
// Other core is now stalled, can access DPORT registers directly
esp_dport_access_int_abort();
// Disable TG0/TG1 watchdogs
TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG0.wdt_config0.en = 0;
TIMERG0.wdt_wprotect=0;
TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE;
TIMERG1.wdt_config0.en = 0;
TIMERG1.wdt_wprotect=0;
// Flush any data left in UART FIFOs
uart_tx_wait_idle(0);
uart_tx_wait_idle(1);
uart_tx_wait_idle(2);
// Disable cache
Cache_Read_Disable(0);
Cache_Read_Disable(1);
// 2nd stage bootloader reconfigures SPI flash signals.
// Reset them to the defaults expected by ROM.
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
// Reset timer/spi/uart
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
// Set CPU back to XTAL source, no PLL, same as hard reset
rtc_clk_cpu_freq_set_xtal();
// Clear entry point for APP CPU
DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
// Reset CPUs
if (core_id == 0) {
// Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
esp_cpu_reset(1);
esp_cpu_reset(0);
} else {
// Running on APP CPU: need to reset PRO CPU and unstall it,
// then reset APP CPU
esp_cpu_reset(0);
esp_cpu_unstall(0);
esp_cpu_reset(1);
}
while(true) {
;
}
}
int digitalLeds_initStrands(strand_t strands [], int numStrands)
{
#if DEBUG_ESP32_DIGITAL_LED_LIB
snprintf(digitalLeds_debugBuffer, digitalLeds_debugBufferSz,
"%sdigitalLeds_init numStrands = %d\n", digitalLeds_debugBuffer, numStrands);
#endif
localStrands = strands;
localStrandCnt = numStrands;
if (localStrandCnt < 1 || localStrandCnt > 8) {
return -1;
}
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_RMT_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST);
RMT.apb_conf.fifo_mask = 1; // Enable memory access, instead of FIFO mode
RMT.apb_conf.mem_tx_wrap_en = 1; // Wrap around when hitting end of buffer
for (int i = 0; i < localStrandCnt; i++) {
strand_t * pStrand = &localStrands[i];
ledParams_t ledParams = ledParamsAll[pStrand->ledType];
pStrand->pixels = static_cast<pixelColor_t*>(malloc(pStrand->numPixels * sizeof(pixelColor_t)));
if (pStrand->pixels == nullptr) {
return -1;
}
pStrand->_stateVars = static_cast<digitalLeds_stateData*>(malloc(sizeof(digitalLeds_stateData)));
if (pStrand->_stateVars == nullptr) {
return -1;
}
digitalLeds_stateData * pState = static_cast<digitalLeds_stateData*>(pStrand->_stateVars);
pState->buf_len = (pStrand->numPixels * ledParams.bytesPerPixel);
pState->buf_data = static_cast<uint8_t*>(malloc(pState->buf_len));
if (pState->buf_data == nullptr) {
return -1;
}
rmt_set_pin(
static_cast<rmt_channel_t>(pStrand->rmtChannel),
RMT_MODE_TX,
static_cast<gpio_num_t>(pStrand->gpioNum));
RMT.conf_ch[pStrand->rmtChannel].conf0.div_cnt = DIVIDER;
RMT.conf_ch[pStrand->rmtChannel].conf0.mem_size = 1;
RMT.conf_ch[pStrand->rmtChannel].conf0.carrier_en = 0;
RMT.conf_ch[pStrand->rmtChannel].conf0.carrier_out_lv = 1;
RMT.conf_ch[pStrand->rmtChannel].conf0.mem_pd = 0;
RMT.conf_ch[pStrand->rmtChannel].conf1.rx_en = 0;
RMT.conf_ch[pStrand->rmtChannel].conf1.mem_owner = 0;
RMT.conf_ch[pStrand->rmtChannel].conf1.tx_conti_mode = 0; //loop back mode
RMT.conf_ch[pStrand->rmtChannel].conf1.ref_always_on = 1; // use apb clock: 80M
RMT.conf_ch[pStrand->rmtChannel].conf1.idle_out_en = 1;
RMT.conf_ch[pStrand->rmtChannel].conf1.idle_out_lv = 0;
RMT.tx_lim_ch[pStrand->rmtChannel].limit = MAX_PULSES;
// RMT config for transmitting a '0' bit val to this LED strand
pState->pulsePairMap[0].level0 = 1;
pState->pulsePairMap[0].level1 = 0;
pState->pulsePairMap[0].duration0 = ledParams.T0H / (RMT_DURATION_NS * DIVIDER);
pState->pulsePairMap[0].duration1 = ledParams.T0L / (RMT_DURATION_NS * DIVIDER);
// RMT config for transmitting a '0' bit val to this LED strand
pState->pulsePairMap[1].level0 = 1;
pState->pulsePairMap[1].level1 = 0;
pState->pulsePairMap[1].duration0 = ledParams.T1H / (RMT_DURATION_NS * DIVIDER);
pState->pulsePairMap[1].duration1 = ledParams.T1L / (RMT_DURATION_NS * DIVIDER);
RMT.int_ena.val |= tx_thr_event_offsets[pStrand->rmtChannel]; // RMT.int_ena.ch<n>_tx_thr_event = 1;
RMT.int_ena.val |= tx_end_offsets[pStrand->rmtChannel]; // RMT.int_ena.ch<n>_tx_end = 1;
}
esp_intr_alloc(ETS_RMT_INTR_SOURCE, 0, handleInterrupt, nullptr, &rmt_intr_handle);
for (int i = 0; i < localStrandCnt; i++) {
strand_t * pStrand = &localStrands[i];
digitalLeds_resetPixels(pStrand);
}
return 0;
}
