示例#1
0
static inline bool dqs_preset(const struct tegra11_emc_table *next_timing,
			      const struct tegra11_emc_table *last_timing)
{
	bool ret = false;

#define DQS_SET(reg, bit)						      \
	do {								      \
		if ((next_timing->burst_regs[EMC_##reg##_INDEX] &	      \
		     EMC_##reg##_##bit##_ENABLE) &&			      \
		    (!(last_timing->burst_regs[EMC_##reg##_INDEX] &	      \
		       EMC_##reg##_##bit##_ENABLE)))   {		      \
			emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \
				   | EMC_##reg##_##bit##_ENABLE, EMC_##reg);  \
			ret = true;					      \
		}							      \
	} while (0)


#define DQS_SET_TRIM(reg, bit, ch)					       \
	do {								       \
		if ((next_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]    \
		     & EMC_##reg##_##bit##_ENABLE) &&			       \
		    (!(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX]  \
		       & EMC_##reg##_##bit##_ENABLE)))   {		       \
			emc##ch##_writel(last_timing->emc_trimmers_##ch[EMC_##reg##_TRIM_INDEX] \
				   | EMC_##reg##_##bit##_ENABLE, EMC_##reg);   \
			ret = true;					       \
		}							       \
	} while (0)

	DQS_SET(XM2DQSPADCTRL2, VREF);

	return ret;
}
static inline bool dqs_preset(const struct tegra_emc_table *next_timing,
			      const struct tegra_emc_table *last_timing)
{
	bool ret = false;

#define DQS_SET(reg, bit)						      \
	do {								      \
		if ((next_timing->burst_regs[EMC_##reg##_INDEX] &	      \
		     EMC_##reg##_##bit##_ENABLE) &&			      \
		    (!(last_timing->burst_regs[EMC_##reg##_INDEX] &	      \
		       EMC_##reg##_##bit##_ENABLE)))   {		      \
			emc_writel(last_timing->burst_regs[EMC_##reg##_INDEX] \
				   | EMC_##reg##_##bit##_ENABLE, EMC_##reg);  \
			ret = true;					      \
		}							      \
	} while (0)

	DQS_SET(XM2DQSPADCTRL2, VREF);
	DQS_SET(XM2DQSPADCTRL3, VREF);
	DQS_SET(XM2QUSEPADCTRL, IVREF);

	return ret;
}