void GPIO_WriteIO(unsigned int data, unsigned int pin)
{
unsigned int no;
unsigned int remainder;
no = pin >>4;
remainder = pin & 0xf ;
if (data == 1)
DRV_WriteReg16(GPIO_DOUT_SET(no),(1 << remainder));
else
DRV_WriteReg16(GPIO_DOUT_CLR(no),(1 << remainder));
}
void mtk_wdt_restart(void)
{
// Reset WatchDogTimer's counting value to time out value
// ie., keepalive()
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
}
void MT6573_wdt_Restart(void)
{
// Reset WatchDogTimer's counting value to default value
// ie., keepalive()
DRV_WriteReg16(MT6573_WDT_RESTART, MT6573_WDT_RESTART_KEY);
}
void MT6573_wdt_ModeSelection(kal_bool en, kal_bool auto_rstart, kal_bool IRQ )
{
unsigned short tmp;
tmp = DRV_Reg16(MT6573_WDT_MODE);
tmp |= MT6573_WDT_MODE_KEY;
// Bit 0 : Whether enable watchdog or not
if(en == KAL_TRUE)
tmp |= MT6573_WDT_MODE_ENABLE;
else
tmp &= ~MT6573_WDT_MODE_ENABLE;
// Bit 4 : Whether enable auto-restart or not for counting value
if(auto_rstart == KAL_TRUE)
tmp |= MT6573_WDT_MODE_AUTORST;
else
tmp &= ~MT6573_WDT_MODE_AUTORST;
// Bit 3 : TRUE for generating Interrupt (False for generating Reset) when WDT timer reaches zero
if(IRQ == KAL_TRUE)
tmp |= MT6573_WDT_RESET_IRQ;
else
tmp &= ~MT6573_WDT_RESET_IRQ;
DRV_WriteReg16(MT6573_WDT_MODE,tmp);
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned short wdt_mode_val;
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg(MTK_WDT_MODE);
/* clear autorestart bit: autoretart: 1, bypass power key, 0: not bypass power key */
wdt_mode_val &=(~MTK_WDT_MODE_AUTO_RESTART);
/* make sure WDT mode is hw reboot mode, can not config isr mode */
wdt_mode_val &=(~(MTK_WDT_MODE_IRQ|MTK_WDT_MODE_ENABLE));
if(mode){ /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
//DRV_WriteReg(MTK_WDT_MODE, wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART));
}else{
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
//DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN));
}
DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_LENGTH, MTK_WDT_LENGTH_KEY);
gpt_busy_wait_us(100);
DRV_WriteReg(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
void uart_setbrg()
{
unsigned int byte,speed;
unsigned int highspeed;
unsigned int quot, divisor, remainder;
unsigned int uartclk;
unsigned short data, high_speed_div, sample_count, sample_point;
unsigned int tmp_div;
speed = g_brg;
uartclk = (unsigned int)(mt6575_get_bus_freq()*1000/4);
if (speed <= 115200 ) {
highspeed = 0;
quot = 16;
} else {
highspeed = 3;
quot = 1;
}
if (highspeed < 3) { /*0~2*/
/* Set divisor DLL and DLH */
divisor = uartclk / (quot * speed);
remainder = uartclk % (quot * speed);
if (remainder >= (quot / 2) * speed)
divisor += 1;
DRV_WriteReg16(UART_HIGHSPEED(g_uart),highspeed);
byte = DRV_Reg32(UART_LCR(g_uart)); /* DLAB start */
DRV_WriteReg32( UART_LCR(g_uart),(byte | UART_LCR_DLAB));
DRV_WriteReg32( UART_DLL(g_uart),(divisor & 0x00ff));
DRV_WriteReg32( UART_DLH(g_uart),((divisor >> 8)&0x00ff));
DRV_WriteReg32( UART_LCR(g_uart),byte); /* DLAB end */
}
void MT6573_sw_watchdog_reset(void)
{
/* Watchdog Rest */
DRV_WriteReg16(MT6573_WDT_RESTART, MT6573_WDT_RESTART_KEY);
DRV_WriteReg(MT6573_WDT_MODE, (MT6573_WDT_MODE_KEY|MT6573_WDT_MODE_EXTEN|MT6573_WDT_MODE_ENABLE));
//DRV_WriteReg(MT6573_WDT_LENGTH, MT6573_WDT_LENGTH_KEY);
DRV_WriteReg(MT6573_WDT_SWRST, MT6573_WDT_SWRST_KEY);
}
void GPIO_InitIO(unsigned int dir, unsigned int pin)
{
unsigned int no,remainder;
no = pin >>4;
remainder = pin & 0xf;
if (dir == OUTPUT)
{
DRV_WriteReg16(GPIO_PULLEN_SET(no),(1 << remainder));
DRV_WriteReg16(GPIO_DIR_SET(no),(1 << remainder));
}
else
{
DRV_WriteReg16(GPIO_PULLEN_CLR(no),(1 << remainder));
DRV_WriteReg16(GPIO_DIR_CLR(no),(1 << remainder));
}
I2C_DUMMY_DELAY(100);
}
DRV_STATUS_CODE DRV_SD_Init(void)
{
#if (defined(__UBL__) || defined(__FUE__)) && defined(MT6256_S00)
// enable GPIO for MSDC
DRV_WriteReg16(0x701D0610, 0x1110);
DRV_WriteReg16(0x701D0620, 0x0111);
// enable GPT3
DRV_WriteReg32(0x7007001C, 1);
#endif
#if !defined(DCL_MSDC_INTERFACE)
MSDC_Initialize();
#else
DclSD_Initialize();
#endif//!defined(DCL_MSDC_INTERFACE)
return DRV_SUCCESS;
}
void MT6573_wdt_SetTimeOutValue(unsigned short value)
{
/*
* TimeOut = BitField 15:5
* Key = BitField 4:0 = 0x08
*/
// sec * 32768 / 512 = sec * 64 = sec * 1 << 6
timeout = (unsigned short)(value * ( 1 << 6) );
timeout = timeout << 5;
DRV_WriteReg16(MT6573_WDT_LENGTH, (timeout | MT6573_WDT_LENGTH_KEY) );
}
void mtk_wdt_set_time_out_value(UINT16 value)
{
/*
* TimeOut = BitField 15:5
* Key = BitField 4:0 = 0x08
*/
// sec * 32768 / 512 = sec * 64 = sec * 1 << 6
timeout = (unsigned short)(value * ( 1 << 6) );
timeout = timeout << 5;
DRV_WriteReg16(MTK_WDT_LENGTH, (timeout | MTK_WDT_LENGTH_KEY) );
}
static void mtk_wdt_mode_config(BOOL debug_en,
BOOL irq,
BOOL ext_en,
BOOL ext_pol,
BOOL wdt_en )
{
unsigned short tmp;
tmp = DRV_Reg16(MTK_WDT_MODE);
tmp |= MTK_WDT_MODE_KEY;
// Bit 0 : Whether enable watchdog or not
if(wdt_en == TRUE)
tmp |= MTK_WDT_MODE_ENABLE;
else
tmp &= ~MTK_WDT_MODE_ENABLE;
// Bit 1 : Configure extern reset signal polarity.
if(ext_pol == TRUE)
tmp |= MTK_WDT_MODE_EXT_POL;
else
tmp &= ~MTK_WDT_MODE_EXT_POL;
// Bit 2 : Whether enable external reset signal
if(ext_en == TRUE)
tmp |= MTK_WDT_MODE_EXTEN;
else
tmp &= ~MTK_WDT_MODE_EXTEN;
// Bit 3 : Whether generating interrupt instead of reset signal
if(irq == TRUE)
tmp |= MTK_WDT_MODE_IRQ;
else
tmp &= ~MTK_WDT_MODE_IRQ;
// Bit 6 : Whether enable debug module reset
if(debug_en == TRUE)
tmp |= MTK_WDT_MODE_DEBUG_EN;
else
tmp &= ~MTK_WDT_MODE_DEBUG_EN;
DRV_WriteReg16(MTK_WDT_MODE,tmp);
}
static void mtk_wdt_reset(char mode)
{
/* Watchdog Rest */
unsigned short wdt_mode_val;
DRV_WriteReg16(MTK_WDT_RESTART, MTK_WDT_RESTART_KEY);
wdt_mode_val = DRV_Reg(MTK_WDT_MODE);
if(mode){ /* mode != 0 means by pass power key reboot, We using auto_restart bit as by pass power key flag */
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART);
DRV_WriteReg(MTK_WDT_MODE, wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN|MTK_WDT_MODE_AUTO_RESTART));
}else{
wdt_mode_val = wdt_mode_val | (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN);
DRV_WriteReg(MTK_WDT_MODE,wdt_mode_val);
//DRV_WriteReg(MTK_WDT_MODE, (MTK_WDT_MODE_KEY|MTK_WDT_MODE_EXTEN));
}
//DRV_WriteReg(MTK_WDT_LENGTH, MTK_WDT_LENGTH_KEY);
gpt_busy_wait_us(100);
DRV_WriteReg(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
}
PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
{
#if !defined(NO_HARDWARE)
SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
{
return PVRSRV_OK;
}
PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) && defined(CONFIG_PM_RUNTIME)
{
int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev);
if (res < 0)
{
PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res));
return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
}
}
#endif
//disable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
//disable_clock(MT65XX_PDN_MM_MFG, "MFG");
//disable_clock(MT65XX_PDN_MM_G3D, "MFG");
#if USE_SYS_CLOCK
#if !defined(MTK_CLK_CTRL)
DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
#endif
DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x4); // MFG_CORE_CK_SEL DCM
#else
#if !defined(MTK_CLK_CTRL)
DRV_WriteReg16(PLL_CON11, DRV_Reg16(PLL_CON11)|0x0C00); // F3D_CK_SEL
#endif
DRV_WriteReg32(MMSYS2_CONFG_BASE + 0x0504, 0x6); // MFG_CORE_CK_SEL DCM
#endif
//DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);
enable_clock(MT65XX_PDN_MM_G3D, "MFG");
enable_clock(MT65XX_PDN_MM_MFG, "MFG");
enable_clock(MT65XX_PDN_MM_MFG_HALF, "MFG");
DRV_WriteReg32(MMSYS2_CONFG_BASE+0x400, DRV_Reg32(MMSYS2_CONFG_BASE+0x400)|0x4);
#if defined(MTK_USE_GDC)
SysInitGDC();
#endif
#if 0
DRV_WriteReg16(0xF0007404, 0x6);
DRV_WriteReg16(0xF0007400, 0x4800);
DRV_WriteReg16(0xF0007400, 0x0800);
DRV_WriteReg16(0xF0007400, 0x8800);
while(DRV_Reg16(0xF0007404) & 0x8000){}
PVRSRVReleasePrintf("MainPLL: 0x%x", DRV_Reg16(0xF0007410));
DRV_WriteReg16(0xF0007404, 0x15);
DRV_WriteReg16(0xF0007400, 0x4800);
DRV_WriteReg16(0xF0007400, 0x0800);
DRV_WriteReg16(0xF0007400, 0x8800);
while(DRV_Reg16(0xF0007404) & 0x8000){}
PVRSRVReleasePrintf("MEMPLL: 0x%x", DRV_Reg16(0xF0007410));
#endif
SysEnableSGXInterrupts(psSysData);
atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
#else
PVR_UNREFERENCED_PARAMETER(psSysData);
#endif
return PVRSRV_OK;
}
kal_uint16 mtk_cpe_one_shot_handler(kal_uint16 path1, kal_uint16 path2, kal_uint16 path3)
{
kal_uint16 count, try_count, ret;
DRV_WriteReg16(CA9_ROSC_CON0, 0x8); // reset the overflow bit of CA9 frequency meter
DRV_WriteReg16(CA9_ROSC_CON0, 0x4); // reset the circuit of CA9 frequency meter
DRV_WriteReg16(CA9_ROSC_MON_CTRL_0, 0x0); // switch back to CA9 control
DRV_WriteReg16(CA9_ROSC_CON3, path1); // CA9 ROSC delay path selection [15:0]
DRV_WriteReg16(CA9_ROSC_CON4, path2); // CA9 ROSC delay path selection [31:16]
DRV_WriteReg16(CA9_ROSC_CON5, path3); // CA9 ROSC delay path selection [47:32]
ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
cpe_dprintk("[before toggling] the CA9 frequency meter value is %d\n", ret);
DRV_WriteReg16(CA9_ROSC_CON0, 0x5); // enable ROSC to start
DRV_WriteReg16(CA9_ROSC_CON1, 0x44); // frequency meter window duration
DRV_WriteReg16(CA9_ROSC_CON2, 0x1); // frequency meter clock divider
DRV_WriteReg16(CA9_ROSC_CON0, 0x7); // reload window duration, enable ROSC to start and start to count
try_count = 5;
ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
while (ret == 0 && try_count--)
{
ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
udelay(10);
}
try_count = 5;
while (try_count--)
{
while (1)
{
ret = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
udelay(10);
if (ret == DRV_Reg16(CA9_ROSC_CON6)) break;
}
ret = DRV_Reg16(CA9_ROSC_CON_STATUS);
if ((ret & CA9_FQMTR_BUSY) == 0)
{
break;
}
else
{
udelay(10);
}
}
ret = DRV_Reg16(CA9_ROSC_CON_STATUS);
if ((ret & CA9_FQMTR_OVERFLOW) == CA9_FQMTR_OVERFLOW)
cpe_dprintk("overflow condition occurred\n");
count = DRV_Reg16(CA9_ROSC_CON6); // CA9 ROSC toggle count during window is high
cpe_dprintk("[after toggling] the CA9 frequency meter value is %d\n", count);
DRV_WriteReg16(CA9_ROSC_MON_CTRL_0, 0x0); // switch back to CA9 control
DRV_WriteReg16(CA9_ROSC_CON0, 0x8); // disable ROSC and reset the overflow bit of CA9 frequency meter
DRV_WriteReg16(CA9_ROSC_CON0, 0x4); // reset the circuit of CA9 frequency meter
return count;
}
int mtk_pmic_dvfs_wrapper_test(int loop_count)
{
int i = 0, try_count = 0, ap_dvfs_con = 0;
//PWRAPFUC();
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR0, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR1, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR2, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR3, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR4, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR5, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR6, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_ADR7, 0x021A);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA0, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA1, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA2, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA3, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA4, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA5, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA6, 0x58);
DRV_WriteReg16(PMIC_WRAP_DVFS_WDATA7, 0x58);
while (loop_count--)
{
for (i = 0; i < 8; i++)
{
ap_dvfs_con = DRV_Reg32(AP_DVFS_CON_SET);
DRV_WriteReg32(AP_DVFS_CON_SET, (ap_dvfs_con & ~(0x7)) | i);
while ((DRV_Reg32(AP_DVFS_CON_SET) & 0x80000000) == 0)
{
try_count++;
if (try_count >= MAX_RETRY_COUNT)
{
switch ( raw_smp_processor_id())
{
case 0:
g_spm_fail_cpu0++;
break;
case 1:
g_spm_fail_cpu1++;
break;
case 2:
g_spm_fail_cpu2++;
break;
case 3:
g_spm_fail_cpu3++;
break;
default:
break;
}
//PWRAPLOG("FAIL: no response from PMIC wrapper\n");
return -1;
}
//PWRAPLOG("wait for PMIC response an ACK signal, retry count = %d\n", try_count);
msleep(10);
}
try_count = 0;
}
}
switch ( raw_smp_processor_id())
{
case 0:
g_spm_pass_cpu0++;
break;
case 1:
g_spm_pass_cpu1++;
break;
case 2:
g_spm_pass_cpu2++;
break;
case 3:
g_spm_pass_cpu3++;
break;
default:
break;
}
//PWRAPLOG("PASS: PMIC DVFS Wrapper stress pass\n");
return 0;
}
