/*FUNCTION********************************************************************** * * Function Name : DSPI_DRV_DmaMasterConfigureBus * Description : Configures the DSPI port physical parameters to access a device on the bus with * DMA support. * * The term "device" is used to indicate the SPI device for which the DSPI master is communicating. * The user has two options to configure the device parameters: either pass in the * pointer to the device configuration structure to the desired transfer function (see * DSPI_DRV_DmaMasterTransferBlocking or DSPI_DRV_DmaMasterTransfer) or pass it in to the * DSPI_DRV_DmaMasterConfigureBus function. The user can pass in a device structure to the * transfer function which contains the parameters for the bus (the transfer function then calls * this function). However, the user has the option to call this function directly especially * to get the calculated baud rate, at which point they may pass in NULL for the device * structure in the transfer function (assuming they have called this configure bus function * first). This is an example to set up the dspi_device_t structure to call * the DSPI_DRV_DmaMasterConfigureBus function by passing in these parameters: * dspi_dma_device_t spiDevice; * spiDevice.dataBusConfig.bitsPerFrame = 16; * spiDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge; * spiDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh; * spiDevice.dataBusConfig.direction = kDspiMsbFirst; * spiDevice.bitsPerSec = 50000; * DSPI_DRV_DmaMasterConfigureBus(instance, &spiDevice, &calculatedBaudRate); * *END**************************************************************************/ dspi_status_t DSPI_DRV_DmaMasterConfigureBus(uint32_t instance, const dspi_dma_device_t * device, uint32_t * calculatedBaudRate) { assert(device); /* instantiate local variable of type dspi_dma_master_state_t and point to global state */ dspi_dma_master_state_t * dspiDmaState = (dspi_dma_master_state_t *)g_dspiStatePtr[instance]; SPI_Type *base = g_dspiBase[instance]; dspi_status_t errorCode = kStatus_DSPI_Success; /* Configure the bus to access the provided device.*/ *calculatedBaudRate = DSPI_HAL_SetBaudRate(base, dspiDmaState->whichCtar, device->bitsPerSec, dspiDmaState->dspiSourceClock); errorCode = DSPI_HAL_SetDataFormat(base, dspiDmaState->whichCtar, &device->dataBusConfig); /* Check bits/frame number */ if (device->dataBusConfig.bitsPerFrame > 16) { errorCode = kStatus_DSPI_OutOfRange; } else { dspiDmaState->bitsPerFrame = device->dataBusConfig.bitsPerFrame; /* update bits/frame */ } return errorCode; }
void SpiFormat(Spi_t *obj, int8_t bits, int8_t cpol, int8_t cpha, int8_t slave) { dspi_data_format_config_t dataConfig; dataConfig.clkPhase = ((cpha != 1) ? kDspiClockPhase_FirstEdge : kDspiClockPhase_SecondEdge); dataConfig.clkPolarity = ( (cpol != 1) ? kDspiClockPolarity_ActiveHigh : kDspiClockPolarity_ActiveLow); dataConfig.direction = kDspiMsbFirst; dataConfig.bitsPerFrame = bits; if (obj->isSlave) { } else { DSPI_HAL_SetDataFormat(obj->Spi, kDspiCtar0, &dataConfig); } }
void spi_format(spi_t *obj, int bits, int mode, spi_bitorder_t order) { dspi_data_format_config_t config = {0}; config.bitsPerFrame = (uint32_t)bits; obj->spi.bits = bits; config.clkPolarity = (mode & 0x2) ? kDspiClockPolarity_ActiveLow : kDspiClockPolarity_ActiveHigh; config.clkPhase = (mode & 0x1) ? kDspiClockPhase_SecondEdge : kDspiClockPhase_FirstEdge; if (order == SPI_MSB) { config.direction = kDspiMsbFirst; } else { config.direction = kDspiLsbFirst; } dspi_status_t result = DSPI_HAL_SetDataFormat(obj->spi.address, kDspiCtar0, &config); if (result != kStatus_DSPI_Success) { error("Failed to configure SPI data format"); } DSPI_HAL_SetMasterSlaveMode(obj->spi.address, kDspiMaster); }
void dspi_slave_setup(uint32_t instance, uint32_t baudrate) { dspi_data_format_config_t config; uint32_t baseAddr = SPI0_BASE; // Enable clock CLOCK_SYS_EnableSpiClock(instance); // Clear flags DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxComplete); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxAndRxStatus); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoDrainRequest); // Enable HAL DSPI_HAL_Init(baseAddr); DSPI_HAL_SetMasterSlaveMode(baseAddr, kDspiSlave); DSPI_HAL_Enable(baseAddr); // Disable transfer DSPI_HAL_StopTransfer(baseAddr); // PCS popularity DSPI_HAL_SetPcsPolarityMode(baseAddr, kDspiPcs0, kDspiPcs_ActiveLow); // CTAR DSPI_HAL_SetBaudRate(baseAddr, kDspiCtar0, baudrate, 72000000); config.bitsPerFrame = 16; config.clkPhase = kDspiClockPhase_FirstEdge; config.clkPolarity = kDspiClockPolarity_ActiveHigh; config.direction = kDspiMsbFirst; DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &config); // Interrupt INT_SYS_EnableIRQ(g_dspiIrqId[instance]); DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow, false); DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest, false); // DMA DSPI_HAL_SetTxFifoFillDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateIntReq, true); DSPI_HAL_SetRxFifoDrainDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateDmaReq, true); }
/*! * @brief DSPI master Polling. * * Thid function uses DSPI master to send an array to slave * and receive the array back from slave, * thencompare whether the two buffers are the same. */ int main(void) { uint32_t i; uint32_t loopCount = 1; SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE; uint32_t dspiSourceClock; uint32_t calculatedBaudRate; dspi_device_t masterDevice; dspi_command_config_t commandConfig = { .isChipSelectContinuous = false, .whichCtar = kDspiCtar0, .whichPcs = kDspiPcs0, .clearTransferCount = true, .isEndOfQueue = false }; // Init hardware hardware_init(); // Init OSA layer, used in DSPI_DRV_MasterTransferBlocking. OSA_Init(); // Call this function to initialize the console UART. This function // enables the use of STDIO functions (printf, scanf, etc.) dbg_uart_init(); // Print a note. printf("\r\n DSPI board to board polling example"); printf("\r\n This example run on instance 0 "); printf("\r\n Be sure DSPI0-DSPI0 are connected "); // Configure SPI pins. configure_spi_pins(DSPI_MASTER_INSTANCE); // Enable DSPI clock. CLOCK_SYS_EnableSpiClock(DSPI_MASTER_INSTANCE); // Initialize the DSPI module registers to default value, which disables the module DSPI_HAL_Init(dspiBaseAddr); // Set to master mode. DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiMaster); // Configure for continuous SCK operation DSPI_HAL_SetContinuousSckCmd(dspiBaseAddr, false); // Configure for peripheral chip select polarity DSPI_HAL_SetPcsPolarityMode(dspiBaseAddr, kDspiPcs0, kDspiPcs_ActiveLow); // Disable FIFO operation. DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false); // Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 DSPI_HAL_SetDelay(dspiBaseAddr, kDspiCtar0, 0, 1, kDspiPcsToSck); // DSPI system enable DSPI_HAL_Enable(dspiBaseAddr); // Configure baudrate. masterDevice.dataBusConfig.bitsPerFrame = 8; masterDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge; masterDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh; masterDevice.dataBusConfig.direction = kDspiMsbFirst; DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &masterDevice.dataBusConfig); // Get DSPI source clock. dspiSourceClock = CLOCK_SYS_GetSpiFreq(DSPI_MASTER_INSTANCE); calculatedBaudRate = DSPI_HAL_SetBaudRate(dspiBaseAddr, kDspiCtar0, TRANSFER_BAUDRATE, dspiSourceClock); printf("\r\n Transfer at baudrate %lu \r\n", calculatedBaudRate); while(1) { // Initialize the transmit buffer. for (i = 0; i < TRANSFER_SIZE; i++) { sendBuffer[i] = i + loopCount; } // Print out transmit buffer. printf("\r\n Master transmit:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", sendBuffer[i]); } // Reset the receive buffer. for (i = 0; i < TRANSFER_SIZE; i++) { receiveBuffer[i] = 0; } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Send the data to slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write data to PUSHR DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, sendBuffer[i]); // Delay to wait slave is ready. OSA_TimeDelay(1); } // Delay to wait slave is ready. OSA_TimeDelay(10); // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); //Clear status flags that may have been set from previous transfers. DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count. DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Receive the data from slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write command to PUSHR. DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, 0); // Check RFDR flag while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false) {} // Read data from POPR receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr); // Clear RFDR flag DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest); // Delay to wait slave is ready. OSA_TimeDelay(1); } // Print out receive buffer. printf("\r\n Master receive:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", receiveBuffer[i]); } // Check receiveBuffer. for (i = 0; i < TRANSFER_SIZE; ++i) { if (receiveBuffer[i] != sendBuffer[i]) { // Master received incorrect. printf("\r\n ERROR: master received incorrect "); return -1; } } printf("\r\n DSPI Master Sends/ Recevies Successfully"); // Wait for press any key. printf("\r\n Press any key to run again"); getchar(); // Increase loop count to change transmit buffer. loopCount++; } }
/*! * @brief DSPI slave Polling. * * This function sends back received buffer from master through DSPI interface. */ int main(void) { uint32_t i; SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE; dspi_slave_user_config_t slaveConfig; // Init hardware hardware_init(); // Init OSA layer, used in DSPI_DRV_MasterTransferBlocking. OSA_Init(); // Call this function to initialize the console UART. This function // enables the use of STDIO functions (printf, scanf, etc.) dbg_uart_init(); // Configure SPI pins. configure_spi_pins(DSPI_SLAVE_INSTANCE); // Print a note. printf("\r\n DSPI board to board polling example"); printf("\r\n This example run on instance 0 "); printf("\r\n Be sure DSPI0-DSPI0 are connected "); // Enable clock for DSPI CLOCK_SYS_EnableSpiClock(DSPI_SLAVE_INSTANCE); // Reset the DSPI module, which also disables the DSPI module DSPI_HAL_Init(dspiBaseAddr); // Set to slave mode. DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiSlave); // Set data format slaveConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge; slaveConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh; slaveConfig.dataConfig.bitsPerFrame = 8; DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &(slaveConfig.dataConfig)); // DSPI system enable DSPI_HAL_Enable(dspiBaseAddr); // Disable FIFO operation. DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false); while(1) { printf("\r\n Slave example is running..."); // Reset the receive buffer. for (i = 0; i < TRANSFER_SIZE; i++) { receiveBuffer[i] = 0; } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); for (i = 0; i < TRANSFER_SIZE; i++) { // Check RFDR flag while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false) {} // Read data from POPR receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr); // Clear RFDR flag DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest); } // Restart the transfer by stop then start again, this will clear out the shift register DSPI_HAL_StopTransfer(dspiBaseAddr); // Flush the FIFOs DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true); // Clear status flags that may have been set from previous transfers DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow); DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest); // Clear the transfer count DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0); // Start the transfer process in the hardware DSPI_HAL_StartTransfer(dspiBaseAddr); // Send the data to slave. for (i = 0; i < TRANSFER_SIZE; i++) { // Write data to PUSHR DSPI_HAL_WriteDataSlavemodeBlocking(dspiBaseAddr, receiveBuffer[i]); } // Print out receive buffer. printf("\r\n Slave receive:"); for (i = 0; i < TRANSFER_SIZE; i++) { // Print 16 numbers in a line. if ((i & 0x0F) == 0) { printf("\r\n "); } printf(" %02X", receiveBuffer[i]); } } }
/************************************************************************* * Function Name: SPI0_init * Parameters: none * Return: none * Description: SPI initialization *************************************************************************/ void SPI0_init(void) { dspi_baud_rate_divisors_t divisors; divisors.doubleBaudRate = 0; divisors.baudRateDivisor = 3; divisors.prescaleDivisor = 3; dspi_data_format_config_t config; config.clkPhase = kDspiClockPhase_SecondEdge; config.bitsPerFrame = 8; config.clkPolarity = kDspiClockPolarity_ActiveHigh; config.direction = kDspiMsbFirst; #if defined(KV10Z7_SERIES) PORT_HAL_SetMuxMode(PORTC_BASE_PTR,2,kPortMuxAsGpio);// MC33937 RESET GPIO_HAL_SetPinDir(GPIOC_BASE_PTR, 2, kGpioDigitalOutput); PORT_HAL_SetMuxMode(PORTD_BASE_PTR,7,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOD_BASE_PTR, 7, kGpioDigitalOutput); #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) PORT_HAL_SetMuxMode(PORTE_BASE_PTR,29,kPortMuxAsGpio);// MC33937 DRV_EN GPIO_HAL_SetPinDir(GPIOE_BASE_PTR, 29, kGpioDigitalOutput); #endif GPIO_HAL_SetPinOutput(GPIOC_BASE_PTR, 2);//MC33937_RESET_HIGH; #if defined(KV10Z7_SERIES) GPIO_HAL_SetPinOutput(GPIOD_BASE_PTR, 7);//MC33937_ENABLE_HIGH; #elif (defined(KV10Z1287_SERIES) || defined(KV11Z7_SERIES)) GPIO_HAL_SetPinOutput(GPIOE_BASE_PTR, 29); #endif DSPI_HAL_StopTransfer(SPI0_BASE_PTR);// halt SPI before SPI setting DSPI_HAL_Enable(SPI0_BASE_PTR);//Enables the DSPI peripheral and sets the MCR MDIS to 0. DSPI_HAL_SetMasterSlaveMode(SPI0_BASE_PTR, kDspiMaster);//Enable Master Mode DSPI_HAL_SetPcsPolarityMode(SPI0_BASE_PTR, kDspiPcs0,kDspiPcs_ActiveLow);//The setting for either "active high, inactive low (0)" or "active low, inactive high(1)" of type dspi_pcs_polarity_config_t. DSPI_HAL_SetFifoCmd(SPI0_BASE_PTR, false, false);//Disable the DSPI FIFOs. DSPI_HAL_PresetTransferCount(SPI0_BASE_PTR, 0x0000);//Pre-sets the transfer count. DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,3,0, kDspiPcsToSck); // CTAR0 selection option for master or slave mode DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,2,0, kDspiLastSckToPcs); DSPI_HAL_SetDelay(SPI0_BASE_PTR, kDspiCtar0,0,2, kDspiAfterTransfer); DSPI_HAL_SetBaudDivisors(SPI0_BASE_PTR, kDspiCtar0, &divisors); DSPI_HAL_SetDataFormat(SPI0_BASE_PTR, kDspiCtar0, &config); DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxComplete);///*!< TCF status/interrupt enable */ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiEndOfQueue);///*!< EOQF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoUnderflow);///*!< TFUF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiTxFifoFillRequest);///*!< TFFF status/interrupt enable*/ DSPI_HAL_ClearStatusFlag(SPI0_BASE_PTR ,kDspiRxFifoOverflow);///*!< RFOF status/interrupt enable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxComplete, false);/*!< TCF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiEndOfQueue, false);/*!< EOQF status/interrupt disable */ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoUnderflow, false);/*!< TFUF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiTxFifoFillRequest, false);/*!< TFFF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoOverflow, false);/*!< RFOF status/interrupt disable*/ DSPI_HAL_SetIntMode(SPI0_BASE_PTR,kDspiRxFifoDrainRequest, false);/*!< RFDF status/interrupt disable*/ DSPI_HAL_StartTransfer(SPI0_BASE_PTR);// Starts the DSPI transfers, clears HALT bit in MCR. PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 3, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTD_BASE_PTR, 2, kPortMuxAlt2); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 0, kPortMuxAlt7); PORT_HAL_SetMuxMode(PORTC_BASE_PTR, 5, kPortMuxAlt2); }