* * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> #include "clock.h" static struct ti_dt_clk dm816x_clks[] = { DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "mpu_ck", "mpu_ck"), DT_CLK(NULL, "timer1_fck", "timer1_fck"), DT_CLK(NULL, "timer2_fck", "timer2_fck"), DT_CLK(NULL, "timer3_fck", "timer3_fck"), DT_CLK(NULL, "timer4_fck", "timer4_fck"), DT_CLK(NULL, "timer5_fck", "timer5_fck"), DT_CLK(NULL, "timer6_fck", "timer6_fck"), DT_CLK(NULL, "timer7_fck", "timer7_fck"), DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"), DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"), DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"), DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"), DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" }, { 0 }, }; const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = { { 0x44e00014, am3_l4_per_clkctrl_regs }, { 0x44e00404, am3_l4_wkup_clkctrl_regs }, { 0x44e00604, am3_mpu_clkctrl_regs }, { 0x44e00800, am3_l4_rtc_clkctrl_regs }, { 0x44e00904, am3_gfx_l3_clkctrl_regs }, { 0x44e00a20, am3_l4_cefuse_clkctrl_regs }, { 0 }, }; static struct ti_dt_clk am33xx_clks[] = { DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"), DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"), DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"), DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"), DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"), DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"), DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"), DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"), DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"), DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"), DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"), { .node_name = NULL }, };
#include <linux/list.h> #include <linux/clk-private.h> #include <linux/clkdev.h> #include <linux/clk/ti.h> #define DRA7_DPLL_ABE_DEFFREQ 180633600 #define DRA7_DPLL_GMAC_DEFFREQ 1000000000 #define DRA7_DPLL_USB_DEFFREQ 960000000 #define DRA7_DPLL_DSP_DEFFREQ 600000000 #define DRA7_DPLL_DSP_GFCLK_NOMFREQ 600000000 #define DRA7_DPLL_EVE_GCLK_NOMFREQ 400000000 #define DRA7_ATL2_DEFFREQ 5644800 static struct omap_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"), DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"), DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"), DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"), DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"), DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"), DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"), DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"), DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"), DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"), DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"), DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"), DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"), DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"), DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
{ DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, { 0 }, }; const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = { { 0x48180500, dm816_default_clkctrl_regs }, { 0x48181400, dm816_alwon_clkctrl_regs }, { 0 }, }; static struct ti_dt_clk dm816x_clks[] = { DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"), DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"), DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"), DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"), { .node_name = NULL }, }; static const char *enable_init_clks[] = { "ddr_pll_clk1", "ddr_pll_clk2", "ddr_pll_clk3", }; int __init dm816x_dt_clk_init(void) { ti_dt_clocks_register(dm816x_clks);
#define OMAP5_DPLL_USB_DEFFREQ 960000000 /* * OMAP5 IVA DPLL frequency settings. The recommended maximum DPLL locked * frequency is 2330 MHz for OPP_LOW & OPP_NOM (value for DPLL_IVA_X2_CLK), * so the DPLL_IVA_DEFFREQ is defined to be half of this value. Note that * the value 1164.8 MHz is chosen so that the DPLL can be locked with proper * M & N divider values. The output clock values are based on the OPP_NOM * frequencies for DSP and IVAHD subsystems. */ #define OMAP5_DPLL_IVA_DEFFREQ 1164800000 #define OMAP5_DSP_GCLK_NOMFREQ 466000000 #define OMAP5_IVA_GCLK_NOMFREQ 388300000 static struct ti_dt_clk omap54xx_clks[] = { DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), DT_CLK(NULL, "sys_clkin", "sys_clkin"), DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"), DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
{ 0x4a008620, dra7_coreaon_clkctrl_regs }, { 0x4a008720, dra7_l3main1_clkctrl_regs }, { 0x4a008a20, dra7_dma_clkctrl_regs }, { 0x4a008b20, dra7_emif_clkctrl_regs }, { 0x4a008c00, dra7_atl_clkctrl_regs }, { 0x4a008d20, dra7_l4cfg_clkctrl_regs }, { 0x4a008e20, dra7_l3instr_clkctrl_regs }, { 0x4a009120, dra7_dss_clkctrl_regs }, { 0x4a009320, dra7_l3init_clkctrl_regs }, { 0x4a009700, dra7_l4per_clkctrl_regs }, { 0x4ae07820, dra7_wkupaon_clkctrl_regs }, { 0 }, }; struct ti_dt_clk dra7xx_compat_clks[] = { DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"), DT_CLK(NULL, "sys_clkin", "sys_clkin1"), DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"), DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"), DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"), DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"), DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"), DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"), DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"), DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"), DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"), DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"), DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"), DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"), DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
idlest_reg->offset &= ~0xf0; idlest_reg->offset |= 0x20; *idlest_bit = AM35XX_ST_IPSS_SHIFT; *idlest_val = OMAP34XX_CM_IDLEST_VAL; } const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = { .allow_idle = omap2_clkt_iclk_allow_idle, .deny_idle = omap2_clkt_iclk_deny_idle, .find_idlest = am35xx_clk_ipss_find_idlest, .find_companion = omap2_clk_dflt_find_companion, }; static struct ti_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"), DT_CLK(NULL, "timer_sys_ck", "sys_ck"), { .node_name = NULL }, }; static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = { DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"), DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"), DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"), DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"), { .node_name = NULL }, }; static struct ti_dt_clk omap3430es1_clks[] = { DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"), DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
* OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK * must be set to 196.608 MHz" and hence, the DPLL locked frequency is * half of this value. */ #define OMAP4_DPLL_ABE_DEFFREQ 98304000 /* * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred * locked frequency for the USB DPLL is 960MHz. */ #define OMAP4_DPLL_USB_DEFFREQ 960000000 static struct ti_dt_clk omap44xx_clks[] = { DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"), DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"), DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"), DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"), DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"), DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"), DT_CLK(NULL, "slimbus_clk", "slimbus_clk"), DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"), DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"), DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"), DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"), DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"), DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"), DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
* modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> static struct ti_dt_clk omap2xxx_clks[] = { DT_CLK(NULL, "func_32k_ck", "func_32k_ck"), DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"), DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"), DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"), DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"), DT_CLK(NULL, "osc_ck", "osc_ck"), DT_CLK(NULL, "sys_ck", "sys_ck"), DT_CLK(NULL, "alt_ck", "alt_ck"), DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), DT_CLK(NULL, "dpll_ck", "dpll_ck"), DT_CLK(NULL, "apll96_ck", "apll96_ck"), DT_CLK(NULL, "apll54_ck", "apll54_ck"), DT_CLK(NULL, "func_54m_ck", "func_54m_ck"),
* modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> static struct ti_dt_clk am33xx_clks[] = { DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"), DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"), DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"), DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"), DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"), DT_CLK(NULL, "tclkin_ck", "tclkin_ck"), DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"), DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"), DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"), DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"), DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"), DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"), DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"), DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
* published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/kernel.h> #include <linux/list.h> #include <linux/clk-provider.h> #include <linux/clk/ti.h> static struct omap_dt_clk omap3xxx_clks[] = { DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"), DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"), DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"), DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"), DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"), DT_CLK("twl", "fck", "osc_sys_ck"), DT_CLK(NULL, "sys_ck", "sys_ck"), DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"), DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"), DT_CLK(NULL, "sys_altclk", "sys_altclk"), DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), DT_CLK(NULL, "sys_clkout1", "sys_clkout1"), DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
{ 0x4a008c20, omap4_d2d_clkctrl_regs }, { 0x4a008d20, omap4_l4_cfg_clkctrl_regs }, { 0x4a008e20, omap4_l3_instr_clkctrl_regs }, { 0x4a008f20, omap4_ivahd_clkctrl_regs }, { 0x4a009020, omap4_iss_clkctrl_regs }, { 0x4a009120, omap4_l3_dss_clkctrl_regs }, { 0x4a009220, omap4_l3_gfx_clkctrl_regs }, { 0x4a009320, omap4_l3_init_clkctrl_regs }, { 0x4a009420, omap4_l4_per_clkctrl_regs }, { 0x4a307820, omap4_l4_wkup_clkctrl_regs }, { 0x4a307a20, omap4_emu_sys_clkctrl_regs }, { 0 }, }; static struct ti_dt_clk omap44xx_clks[] = { DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"), /* * XXX: All the clock aliases below are only needed for legacy * hwmod support. Once hwmod is removed, these can be removed * also. */ DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"), DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"), DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"), DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"), DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"), DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"), DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"), DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"), DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"), DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),