void psxRcntUpdate() { u32 cycle; cycle = psxRegs.cycle; // rcnt 0. if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) { psxRcntReset( 0 ); } // rcnt 1. if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) { psxRcntReset( 1 ); } // rcnt 2. if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) { psxRcntReset( 2 ); } // rcnt base. if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) { psxRcntReset( 3 ); spuSyncCount++; hSyncCount++; // Update spu. if( spuSyncCount >= SpuUpdInterval[Config.PsxType] ) { spuSyncCount = 0; if( SPU_async ) { SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target ); } } // VSync irq. if( hSyncCount == VBlankStart[Config.PsxType] ) { GPU_vBlank( 1 ); // For the best times. :D //setIrq( 0x01 ); } // Update lace. (with InuYasha fix) if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) ) { hSyncCount = 0; GPU_vBlank( 0 ); setIrq( 0x01 ); GPU_updateLace(); EmuUpdate(); } } #ifndef LIBXENON DebugVSync(); #endif }
void psxRcntUpdate() { u32 cycle; cycle = psxRegs.cycle; // rcnt 0. if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle ) { psxRcntReset( 0 ); } // rcnt 1. if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle ) { psxRcntReset( 1 ); } // rcnt 2. if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle ) { psxRcntReset( 2 ); } // rcnt base. if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle ) { psxRcntReset( 3 ); GPU_hSync(hSyncCount); spuSyncCount++; hSyncCount++; // Update spu. if( spuSyncCount >= SpuUpdInterval[Config.PsxType] ) { spuSyncCount = 0; if( SPU_async ) { SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target ); } } #ifdef ENABLE_SIO1API if( SIO1_update ) { SIO1_update( 0 ); } #endif // VSync irq. if( hSyncCount == VBlankStart[Config.PsxType] ) { GPU_vBlank( 1 ); // For the best times. :D //setIrq( 0x01 ); } // Update lace. (calculated at psxHsyncCalculate() on init/defreeze) if( hSyncCount >= HSyncTotal[Config.PsxType] ) { hSyncCount = 0; GPU_vBlank( 0 ); setIrq( 0x01 ); GPU_updateLace(); EmuUpdate(); } } DebugVSync(); }