/*******************************************************************************
**函 数： Standby_Mode
**功 能： 开启待机模式
**参 数： void
**返 回： void
**说 明： 片外模块电源需要在此函数内部关闭
*******************************************************************************/
void Standby_Mode(void)
{
/*关中断*/
SysTick->CTRL = 0; //禁止Systick中断
NVIC_DisableIRQ(EXTI15_10_IRQn); //禁止Si4432中断
DisableIRQ(); //禁止所有用户中断
PowerOFF_LED; //关闭背光灯电源
OLED_POW_0; //关闭OLED电源
RF_SWITCH_OFF; //关闭433电源
SPI2->CR1 &= ~(1<<6); //关闭SPI2
RCC->APB1ENR &= ~(1<<14); //关闭SPI2时钟
RCC->APB2ENR &= ~(1<<14); //关闭USART1时钟
RCC->AHBRSTR |= 1<<0; //Reset GPIOA
RCC->APB1ENR |= 1<<28; //使能电源时钟
/* Set SLEEPDEEP bit : Select SleepDeep mode*/
SCB->SCR|= SCB_SCR_SLEEPDEEP;
/* Set PDDS bit : Select STANDBY mode */
PWR->CR |= PWR_CR_PDDS;
/* Set CWUF bit : Clear Wakeup flag */
PWR->CR |= PWR_CR_CWUF;
/* Set EWUP1 bit : Enable EWUP pin 1 :PA0*/
PWR->CSR|= PWR_CSR_EWUP1;
/* Request Wait For Interrupt */
__WFI();
}
static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg)
{
struct imxrt_uart *uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct imxrt_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable interrupt */
LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
/* disable rx irq */
DisableIRQ(uart->irqn);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable interrupt */
LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
/* enable rx irq */
EnableIRQ(uart->irqn);
break;
}
return RT_EOK;
}
void __init s5c7375_init_irq(void)
{
int irq;
/* Disable all IRQs */
rINTMSK = 0xffffffff; /* all masked */
/****************
* All IRQs are IRQ, not FIQ
* Write only one register,
* 0 : IRQ mode
* 1 : FIQ mode
*******************************************/
rINTMOD = 0x00000000;
for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &s5c7375_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
rINTCON = 0x0; // all interrupt is disabled
// rINTCON = 0xD; // vectored mode
DisableFIQ(); // fiq is disabled
#ifndef CONFIG_S5C7375VM
EnableIRQ(); // irq is enabled
#else
DisableIRQ();
#endif
DisableGMask(); // global mask is disabled
}
void DMIC_HwvadDisableIntCallback(DMIC_Type *base, dmic_hwvad_callback_t vadcb)
{
uint32_t instance;
instance = DMIC_GetInstance(base);
DisableIRQ(s_dmicHwvadIRQ[instance]);
s_dmicHwvadCallback[instance] = NULL;
NVIC_ClearPendingIRQ(s_dmicHwvadIRQ[instance]);
}
void GINT_DisableCallback(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
DisableIRQ(s_gintIRQ[instance]);
GINT_ClrStatus(base);
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
}
void CInterruptSystem::DisconnectIRQ (unsigned nIRQ)
{
assert (nIRQ < IRQ_LINES);
assert (m_apIRQHandler[nIRQ] != 0);
DisableIRQ (nIRQ);
m_apIRQHandler[nIRQ] = 0;
m_pParam[nIRQ] = 0;
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t index = 0;
uint32_t intNumber = (uint32_t)interrupt;
while (intNumber >= 32u)
{
index++;
intNumber -= 32u;
}
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
/*************************************************************************
* FUNCTION
* EINT_SW_Debounce_Modify
*
* DESCRIPTION
* Setting debounce time
*
* CALLS
*
* PARAMETERS
*
* RETURNS
* No return
*
* GLOBALS AFFECTE
*
*************************************************************************/
kal_int32 EINT_SW_Debounce_Modify(kal_uint8 eintno, kal_uint8 debounce_time)
{
kal_uint32 savedMask;
if ( eintno>=EINT_MAX_CHANNEL )
return -1;
savedMask = DisableIRQ();
eint_sw_debounce_time_delay[eintno] = debounce_time;
RestoreIRQ(savedMask);
return 1;
}
void PINT_DisableCallback(PINT_Type *base)
{
uint32_t i;
assert(base);
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
{
DisableIRQ(s_pintIRQ[i]);
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
}
}
void CTIMER_Deinit(CTIMER_Type *base)
{
uint32_t index = CTIMER_GetInstance(base);
/* Stop the timer */
base->TCR &= ~CTIMER_TCR_CEN_MASK;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the timer clock*/
CLOCK_DisableClock(s_ctimerClocks[index]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Disable IRQ at NVIC Level */
DisableIRQ(s_ctimerIRQ[index]);
}
boolean CInterruptSystem::CallIRQHandler (unsigned nIRQ)
{
assert (nIRQ < IRQ_LINES);
TIRQHandler *pHandler = m_apIRQHandler[nIRQ];
if (pHandler != 0)
{
(*pHandler) (m_pParam[nIRQ]);
return TRUE;
}
else
{
DisableIRQ (nIRQ);
}
return FALSE;
}
void SendCharBlock(uart_regs * uart, char c) {
volatile uint32_t tempHead;
uint32_t Idx = GetUartIdx(uart);
tempHead = UartData[Idx].TxIdxHead;
/* calculate new buffer index */
tempHead = ((tempHead + 1) & (UART_TX_BUFFER_SIZE - 1));
while (tempHead == UartData[Idx].TxIdxTail);
DisableIRQ();
WRITE_INT(DSO_SFR_BASE_ADDR,50);
/* add new item to buffer */
UartData[Idx].TxBuf[tempHead] = c;
UartData[Idx].TxIdxHead = tempHead;
/* activate isr to transmit data */
uart->control = (uart->control) | TX_FIFO_INT;
WRITE_INT(DSO_SFR_BASE_ADDR,51);
ReleaseIRQ();
}
int hal_uart_close(int port)
{
struct hal_uart *u;
if (port >= FSL_FEATURE_SOC_UART_COUNT) {
return -1;
}
u = &uarts[port];
if (!u->u_open) {
return -1;
}
u->u_open = 0;
UART_DisableInterrupts(u->u_base, kUART_RxDataRegFullInterruptEnable | kUART_RxOverrunInterruptEnable | kUART_TxDataRegEmptyInterruptEnable);
DisableIRQ(u->u_irq);
UART_EnableTx(u->u_base, false);
UART_EnableRx(u->u_base, false);
return 0;
}
static void SDHC_SetTransferInterrupt(SDHC_Type *base, bool usingInterruptSignal)
{
uint32_t interruptEnabled; /* The Interrupt status flags to be enabled */
sdhc_dma_mode_t dmaMode = (sdhc_dma_mode_t)((base->PROCTL & SDHC_PROCTL_DMAS_MASK) >> SDHC_PROCTL_DMAS_SHIFT);
bool cardDetectDat3 = (bool)(base->PROCTL & SDHC_PROCTL_D3CD_MASK);
/* Disable all interrupts */
SDHC_DisableInterruptStatus(base, (uint32_t)kSDHC_AllInterruptFlags);
SDHC_DisableInterruptSignal(base, (uint32_t)kSDHC_AllInterruptFlags);
DisableIRQ(s_sdhcIRQ[SDHC_GetInstance(base)]);
interruptEnabled =
(kSDHC_CommandIndexErrorFlag | kSDHC_CommandCrcErrorFlag | kSDHC_CommandEndBitErrorFlag |
kSDHC_CommandTimeoutFlag | kSDHC_CommandCompleteFlag | kSDHC_DataTimeoutFlag | kSDHC_DataCrcErrorFlag |
kSDHC_DataEndBitErrorFlag | kSDHC_DataCompleteFlag | kSDHC_AutoCommand12ErrorFlag);
if (cardDetectDat3)
{
interruptEnabled |= (kSDHC_CardInsertionFlag | kSDHC_CardRemovalFlag);
}
switch (dmaMode)
{
case kSDHC_DmaModeAdma1:
case kSDHC_DmaModeAdma2:
interruptEnabled |= (kSDHC_DmaErrorFlag | kSDHC_DmaCompleteFlag);
break;
case kSDHC_DmaModeNo:
interruptEnabled |= (kSDHC_BufferReadReadyFlag | kSDHC_BufferWriteReadyFlag);
break;
default:
break;
}
SDHC_EnableInterruptStatus(base, interruptEnabled);
if (usingInterruptSignal)
{
SDHC_EnableInterruptSignal(base, interruptEnabled);
}
}
static int BURNT_action(int argc, char *argv[])
{
UINT i;
UINT32 src_addr=0x100000;
UINT32 dest_addr=FLASH_BASE;
UINT32 src,dest;
UINT32 fileSize=0;
UINT32 blockSize=0;
INT flash_type;
if( !_net_init )
{
if( Net_Init(_dhcp) < 0 )
{
uprintf("ERROR: Network initialization failed!\n");
return -1;
}
_net_init=1;
}
uprintf("Waiting for download ...\n");
if( TFTP_Download((UCHAR *)src_addr,(ULONG *)&fileSize,_dhcp)==0 )
{
uprintf("\nFlash programming ");
if( _net_init )DisableIRQ();
flash_type=FindFlash();
if( _net_init )EnableIRQ();
if( flash_type < 0 )
{
uprintf("ERROR: Un-supported flash type !!\n");
return -1;
}
// Write program
if( (fileSize&0x3) )fileSize=((fileSize&(~0x3))+4);//word-aligment
i=fileSize;
src=src_addr;
dest=dest_addr;
while(i)
{
blockSize=flash[flash_type].BlockSize(dest);
if( _net_init )DisableIRQ();
flash[flash_type].BlockErase(dest, blockSize);
if( i < blockSize )
{
flash[flash_type].BlockWrite(dest, (UCHAR *)src, i);
blockSize=i;
}
else
{
flash[flash_type].BlockWrite(dest, (UCHAR *)src, blockSize);
}
if( _net_init )EnableIRQ();
src+=blockSize;
dest+=blockSize;
i-=blockSize;
uprintf(".");
}
uprintf(" OK!\n");
}
else
{
uprintf("\nDownload error!\n");
return -1;
}
// verify data
uprintf("Write data verifing ");
for(i=0;i<fileSize;i+=4)
{
if( (i&0xFFFF)== 0x0 )uprintf(".");
if( *((volatile unsigned int *)(src_addr+i))!=*((volatile unsigned int *)(dest_addr+i)) )
{
uprintf("ERROR: Data failed @ 0x%08x \n", dest_addr+i);
return -1;
}
}
uprintf(" OK!\n");
return 0;
}
void L1SP_D2C_LISR( uint16 itype )
{
l1audio.d2c_itype = itype;
l1audio.d2c_l1FN = L1I_GetTimeStamp();
L1Audio_Msg_DSP_INT( itype );
#if __DSP_WAKEUP_EVENT__
Audio_DSP_Wakeup_Eevent_clean();
#endif
#if defined(MT6268) //work around in 3G, there is DP_D2C_SE_DONE int. There might be error operate especially when InterRAT HO
if( itype == DP_D2C_SE_DONE && AM_IsSpeechOn() )
return;
#endif
#if defined(MT6236) || defined(MT6236B) || defined(MT6256_S00) || defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250) || defined(MT6260)
if(itype == D2C_DSP_DEAD_INT_ID){
#ifndef L1D_TEST
{
ASSERT_DUMP_PARAM_T dump_param;
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x0A0*2);
dump_param.len[0] = 70*2;
dump_param.addr[1] = (kal_uint32)(DPRAM2_CPU_base+0x130*2);
dump_param.len[1] = 180*2;
dump_param.addr[2] = 0; //End of dump param
EXT_ASSERT_DUMP(0, 0x20060622, 0, 0, &dump_param);
}
#else
{
extern void L1DTest_AssertFail(void);
L1DTest_AssertFail();
}
#endif
}
#endif // #if defined(MT6236) || defined(MT6236B) || defined(MT6256)
#if defined(MT6260)
{
bool dsp_ok = false;
uint32 sph_int = 0;
bool from_sph = Pseudo_SAL_DSPINT_Resolve(itype, &sph_int);
if (from_sph)
{
{
kal_int16 i;
for (i = 1; i < PSEUDO_SAL_DSPINT_PRIO_MAX; i++)
{
if (sph_int & (1 << i))
{
if (PSEUDO_SAL_DSPINT_PRIO_3G_DL == i)
{
// Do nothing. Don't trigger LISR here. 3G driver will trigger HISR by it's timing
}
else
{
L1Audio_TrigD2CHisr(DP_D2C_INT_MAPPING_BASIC + i);
}
dsp_ok |= true;
}
}
}
// After DSP send D2C and turn on bit in DP_D2C_SPEECH_UL_INT, but MCU does not receive D2C.
// Handover causes VBI reset which will clean DP_D2C_SPEECH_UL_INT
if (sph_int != 0)
{
if (!dsp_ok)
{
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
L1D_WIN_DisableAllEvents(0); // disable all TDMA events
ASSERT_REBOOT(0);
}
}
return;
}
}
L1Audio_TrigD2CHisr(itype);
#else // chip compile option
#if defined(MT6236) || defined(MT6236B) || defined(MT6256_S00) || defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250)
if(itype == D2C_INT6_MAGIC){
bool dsp_ok = false;
#else
if(itype == D2C_DSP_DEAD_INT_ID){
bool dsp_ok = false;
itype = *DSP_DEAD_INTERRUPT;
if( itype == D2C_DSP_DEAD_INT_ID ) {
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
*DP_D2C_TASK1 = 0; /* freeze DSP */
L1D_WIN_DisableAllEvents( 0 ); /* disable all TDMA events */
#ifndef L1D_TEST
{
ASSERT_DUMP_PARAM_T dump_param;
/* Write DSP debug info to exception record */
#if defined(MT6235) || defined(MT6235B) || defined(MT6268) || defined(MT6251)
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x0A0*2);
dump_param.len[0] = 70*2;
dump_param.addr[1] = (kal_uint32)(DPRAM2_CPU_base+0x130*2);
dump_param.len[1] = 180*2;
dump_param.addr[2] = 0; //End of dump param
#else
dump_param.addr[0] = (kal_uint32)(DPRAM_CPU_base +0x130*2);
dump_param.len[0] = 250*2;
dump_param.addr[1] = 0; //End of dump param
#endif
EXT_ASSERT_DUMP(0, 0x20060622, 0, 0, &dump_param);
}
#else
{
extern void L1DTest_AssertFail(void);
L1DTest_AssertFail();
}
#endif//#ifndef L1D_TEST
}
#endif // #if defind(MT6236)|| defined(MT6256)
#if defined(MT6250)
itype = *DSP_DACA_UL_INT;
if(itype == DP_D2C_DACA_REQ_UL){
*DSP_DACA_UL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
itype = *DSP_DACA_DL_INT;
if(itype == DP_D2C_DACA_REQ_DL){
*DSP_DACA_DL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
itype = *DSP_PCM_REC_INT;
if( itype == D2C_UL_DL_PCM_REC_INT_ID || itype == D2C_WAV_REC_REQ_ID )
{
*DSP_PCM_REC_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
itype = *DSP_SOUND_EFFECT_INT;
if( itype == D2C_SOUND_EFFECT_INT_ID )
{
*DSP_SOUND_EFFECT_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#if defined( __BT_AUDIO_VIA_SCO__ ) && !defined(__CVSD_CODEC_SUPPORT__)
itype = *DP_AUDIO_VIA_8KBT_INT;
if( itype == D2C_AUDIO_VIA_8KBT_ID )
{
*DP_AUDIO_VIA_8KBT_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
#if _SPE_FOR_TEST_SIM_
itype = *DP2_ADAPT_VOL_INT;
if( itype == DP_D2C_ADAPT_VOL )
{
*DP2_ADAPT_VOL_INT = 0;
L1SP_D2C_LISR(itype);
dsp_ok |= true;
}
#endif
if (!dsp_ok) {
extern void L1D_WIN_DisableAllEvents(uint16 except_irq_mask);
DisableIRQ();
#if !defined(MT6256_S01) && !defined(MT6255) && !defined(MT6250) && !defined(MT6260)
*DP_D2C_TASK1 = 0; /* freeze DSP */
#endif
L1D_WIN_DisableAllEvents( 0 ); /* disable all TDMA events */
ASSERT_REBOOT(0);
}
return;
}
if( (itype == DP_D2C_SE_SD_DONE) && (!AM_IsSpeechOn()) ) // when idle 16kPCM, AMR/AWB/VM record, the driver expects the D2C_SE_DONE interrupt triggered by DSP. If System's doing SMS, howerver, DSP triggers the D2C_SE_SD_DONE to MCU. Even if in this case, because the data provided by DSP is also available, the drive just easily modifies the interrupt ID to access data provide by DSP.
itype = DP_D2C_SE_DONE;
{
int32 I;
for (I = 0; I < MAX_HISR_HANDLER; I++)
{
if (itype == l1audio.hisrMagicNo[I])
{
l1audio.hisrMagicFlag |= (1<<I);
kal_activate_hisr(l1audio.hisr);
return;
}
}
}
#endif // chip compile option
#if defined(MT6235) || defined(MT6235B) || defined(MT6268) || defined(MT6253) || defined(MT6236) || defined(MT6236B) || defined(MT6256_S00)|| defined(MT6256_S01) || defined(MT6251) || defined(MT6253E) || defined(MT6253L)|| defined(MT6252) || defined(MT6252H) || defined(MT6255) || defined(MT6250) || defined(MT6260)
if (itype == DP_D2C_AVSYNC) {
Media_A2V_LISR();
} else
#endif
{
l1audio.media_flag = itype;
kal_activate_hisr(l1audio.hisr);
}
}
void L1Audio_HookHisrHandler( kal_uint16 magic_no, L1Audio_EventHandler handler, void *userData )
{
int32 I;
for( I = 0; I < MAX_HISR_HANDLER; I++ ) {
if( l1audio.hisrMagicNo[I] == 0 ) {
l1audio.hisrMagicNo[I] = magic_no;
l1audio.hisrHandler[I] = handler;
l1audio.hisrUserData[I] = userData;
break;
}
}
ASSERT_REBOOT( I != MAX_HISR_HANDLER );
}
void isrC_Main(void)
{
kal_uint32 irqx;
void *processing_lisr_backup;
kal_uint16 processing_irqx_backup;
irqx = IRQ_Status();
if(irqx== -1)
return;
processing_lisr_backup = processing_lisr;
processing_irqx_backup = processing_irqx;
processing_irqx = irqx;
processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler;
processing_irqCnt++;
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
#ifdef __SWDBG_SUPPORT__
*SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000;
#endif /* __SWDBG_SUPPORT__ */
#ifdef __WAKEUP_IRQ_DEBUG__
if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) {
wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx;
wkup_intr_log_indx++;
if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) {
wkup_intr_log_indx = 0;
}
}
if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) {
if (wake_tm_name != NULL) {
wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name;
wake_tm_name = NULL;
wkup_timer_log_indx++;
if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) {
wkup_timer_log_indx = 0;
}
}
}
#endif /* __WAKEUP_IRQ_DEBUG__ */
#if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__)
if(TimerHISR_State == 1)
{
GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time);
TimerHISR_State = 2;
}
#endif
#if defined(__TP_SUPPORT_TIMING_CHECK__)
if(Thread_Protect_State==1)
{
Thread_Protect_State=2;
TP_Exclude_Start_Time = ust_get_current_time();
}
#endif
#ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__
demp_preempt_time_start();
#endif
ReEnableIRQ();
lisr_dispatch_tbl[irqx].lisr_handler();
DisableIRQ();
/* restore global variable processing_lisr and processing_irqx to value of preempted IRQ */
processing_irqx = processing_irqx_backup;
processing_lisr = processing_lisr_backup;
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_END_CSM(0xaaaaaaaa);
if( processing_irqx != IRQ_NOT_LISR_CONTEXT )
{
LMU_Write_ISR_RESUME_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaaaaaa);
}
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
/* Binary-coded IRQ idx */
SYS_ClearInt2((kal_uint8)irqx);
}
/*************************************************************************
* FUNCTION
* isrC_Main
*
* DESCRIPTION
* This function implement IRQ's LISR main dispatch routine
*
* CALLS
*
* CALL BY
* INT_IRQ_Parse()
*
* PARAMETERS
*
* RETURNS
*
*************************************************************************/
#if !defined(__SSDVT_TEST__)
#if defined(MT6290) && defined(__ARM7EJ_S__)
void DEVDRV_LS_COPRO_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#else /* defined(MT6290) && defined(__ARM7EJ_S__) */
void DEVDRV_LS_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx)
#endif /* else of "defined(MT6290) && defined(__ARM7EJ_S__)" */
{
#if defined(__UNIFIED_ISR_LEVEL__)
// kal_hisr processing_ehisrid;
kal_hisrid processing_hisrid;
#else /* __UNIFIED_ISR_LEVEL__ */
void *processing_lisr_backup;
kal_uint16 processing_irqx_backup;
processing_lisr_backup = processing_lisr;
processing_irqx_backup = processing_irqx;
#endif /* __UNIFIED_ISR_LEVEL__ */
processing_irqx = irqx;
processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler;
processing_irqCnt++;
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx));
}
CPU_SET_CONTEXT_ID(0xaaaa0000 | ((kal_uint32)processing_irqx));
#ifdef __SWDBG_SUPPORT__
*SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000;
#endif /* __SWDBG_SUPPORT__ */
#ifdef __WAKEUP_IRQ_DEBUG__
if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) {
wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx;
wkup_intr_log_indx++;
if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) {
wkup_intr_log_indx = 0;
}
}
if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) {
if (wake_tm_name != NULL) {
wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name;
wake_tm_name = NULL;
wkup_timer_log_indx++;
if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) {
wkup_timer_log_indx = 0;
}
}
}
#endif /* __WAKEUP_IRQ_DEBUG__ */
#if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__)
if(TimerHISR_State == 1)
{
GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time);
TimerHISR_State = 2;
}
#endif
#if defined(__TP_SUPPORT_TIMING_CHECK__)
if(Thread_Protect_State==1)
{
Thread_Protect_State=2;
TP_Exclude_Start_Time = ust_get_current_time();
}
#endif
#ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__
demp_preempt_time_start();
#endif
#if defined(__UNIFIED_ISR_LEVEL__)
// processing_ehisrid = intrID2hisrEID[irqx];
// ASSERT(0xFF != processing_ehisrid);
// processing_hisrid = hisrid_g[processing_ehisrid];
processing_hisrid = intrID2hisrID[irqx];
if(processing_hisrid != drv_hisr)
{
EXT_ASSERT(NULL != processing_hisrid, irqx, processing_irqCnt, (kal_uint32)processing_lisr);
kal_activate_hisr(processing_hisrid);
}
else
{
drv_active_hisr(irqx);
}
/* no nested interrupt */
processing_lisr = NULL;
processing_irqx = IRQ_NOT_LISR_CONTEXT;
#else /* __UNIFIED_ISR_LEVEL__ */
ReEnableIRQ();
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_enter_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_enter_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
lisr_dispatch_tbl[irqx].lisr_handler(irqx);
#if defined(__CR4__)
IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_leave_time[irqx]));
#elif defined(__MTK_MMU_V2__)
IFDEF_LISR_MEASURE_TIME(lisr_leave_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE());
#endif
DisableIRQ();
processing_irqx = processing_irqx_backup;
processing_lisr = processing_lisr_backup;
#endif /* __UNIFIED_ISR_LEVEL__ */
if (KAL_FALSE == SLA_IsLmuLogging())
{
LMU_Write_ISR_END_CSM(0xaaaaaaaa);
}
if (SA_LoggingIndex != 0)
{
SLA_LoggingLISR(0xaaaaaaaa);
}
CPU_SET_CONTEXT_ID(0xaaaaaaaa);
#if defined __MALMO_ASM_SWTR__
ST_MALMO_ASM_ChangeContextID();
#endif /* __MALMO_ASM_SWTR */
/* Binary-coded IRQ idx */
SYS_endIsr((kal_uint8)irqx);
}
