static BOOL
TSP_VirtualAlloc(VOID)
{
BOOL bRet = TRUE;
TSPMSG((_T("[TSP] ++TSP_VirtualAlloc()\r\n")));
g_pGPIOReg = (S3C6400_GPIO_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_GPIO, sizeof(S3C6400_GPIO_REG), FALSE);
if (g_pGPIOReg == NULL)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : g_pGPIOReg Allocation Fail\r\n")));
bRet = FALSE;
goto CleanUp;
}
g_pADCReg = (S3C6400_ADC_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_ADC, sizeof(S3C6400_ADC_REG), FALSE);
if (g_pADCReg == NULL)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : g_pADCReg Allocation Fail\r\n")));
bRet = FALSE;
goto CleanUp;
}
g_pVIC0Reg = (S3C6400_VIC_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_VIC0, sizeof(S3C6400_VIC_REG), FALSE);
if (g_pVIC0Reg == NULL)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : g_pVIC0Reg Allocation Fail\r\n")));
bRet = FALSE;
goto CleanUp;
}
g_pVIC1Reg = (S3C6400_VIC_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_VIC1, sizeof(S3C6400_VIC_REG), FALSE);
if (g_pVIC1Reg == NULL)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : g_pVIC1Reg Allocation Fail\r\n")));
bRet = FALSE;
goto CleanUp;
}
g_pPWMReg = (S3C6400_PWM_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_PWM, sizeof(S3C6400_PWM_REG), FALSE);
if (g_pPWMReg == NULL)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : g_pPWMReg Allocation Fail\r\n")));
bRet = FALSE;
goto CleanUp;
}
CleanUp:
if (bRet == FALSE)
{
TSPERR((_T("[TSP:ERR] TSP_VirtualAlloc() : Failed\r\n")));
TSP_VirtualFree();
}
TSPMSG((_T("[TSP] --TSP_VirtualAlloc() = %d\r\n"), bRet));
return bRet;
}
virtual BOOL Init()
{
PHYSICAL_ADDRESS ioPhysicalBase = { S3C6400_BASE_REG_PA_GPIO, 0};
ULONG inIoSpace = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
// Map it if it is Memeory Mapped IO.
m_pIOPregs = (S3C6400_GPIO_REG *)DrvLib_MapIoSpace(ioPhysicalBase.LowPart , sizeof(S3C6400_GPIO_REG),FALSE);
}
ioPhysicalBase.LowPart = S3C6400_BASE_REG_PA_SYSCON;
ioPhysicalBase.HighPart = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
m_pSysconRegs = (S3C6400_SYSCON_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart ,sizeof(S3C6400_SYSCON_REG),FALSE);
}
if(m_pSysconRegs)
{
m_pSysconRegs->PCLK_GATE |= (1<<1); // UART0
m_pSysconRegs->SCLK_GATE |= (1<<5); // UART0~3
}
if (m_pIOPregs)
{
DDKISRINFO ddi;
if (GetIsrInfo(&ddi)== ERROR_SUCCESS &&
KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
{
//RETAILMSG( TRUE, (TEXT("DEBUG: Serial0 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr));
RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
}
else
{
return FALSE;
}
m_pDTRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_pDSRPort = (volatile ULONG *)&(m_pIOPregs->GPNDAT);
m_dwDTRPortNum = 6;
m_dwDSRPortNum = 7;
// CTS0(GPA2), RTS0(GPA3), TXD0(GPA1), RXD0(GPA0)
m_pIOPregs->GPACON &= ~(0xf<<0 | 0xf<<4 | 0xf<<8 | 0xf<<12 ); ///< Clear Bit
m_pIOPregs->GPACON |= (0x2<<0 | 0x2<<4 | 0x2<<8 | 0x2<<12 ); ///< Select UART IP
m_pIOPregs->GPAPUD &= ~(0x3<<0 | 0x3<<2 | 0x3<<4 | 0x3<<6 ); ///< Pull-Up/Down Disable
// DTR0(GPN6), DSR0(GPN7)
// If you want to use COM1 port for ActiveSync, use these statements.
m_pIOPregs->GPNCON &= ~(0x3<<12); ///< DTR0 Clear Bit
m_pIOPregs->GPNCON |= (0x1<<12); ///< Output
m_pIOPregs->GPNPUD &= ~(0x3<<12); ///< Pull-Up/Down Disable
m_pIOPregs->GPNCON &= ~(0x3<<14); ///< DSR0 Clear Bit
m_pIOPregs->GPNCON |= (0x0<<14); ///< Input
m_pIOPregs->GPNPUD &= ~(0x3<<14); ///< Pull-Up/Down Disable
return CPdd6400Uart::Init();
}
return FALSE;
}
static BOOL mfc_clock_on_off(int on_off)
{
static volatile S3C6400_SYSCON_REG * pSysConReg = NULL;
// SYSCON_REG register address mapping
// Once it is mapped, it keeps the mapping until the OS is rebooted.
if (pSysConReg == NULL) {
pSysConReg = (S3C6400_SYSCON_REG *)DrvLib_MapIoSpace(S3C6400_BASE_REG_PA_SYSCON, sizeof(S3C6400_SYSCON_REG), FALSE);
if (pSysConReg == NULL)
{
RETAILMSG(1, (L"[[MFC Driver] MFC_Init() : g_pSysConReg DrvLib_MapIoSpace() Failed\n\r"));
return FALSE;
}
}
if (on_off == 0) {
pSysConReg->HCLK_GATE |= (0<<0); // MFC
pSysConReg->PCLK_GATE |= (0<<0); // MFC
pSysConReg->SCLK_GATE |= (0<<3); // MFC
}
else {
pSysConReg->HCLK_GATE |= (1<<0); // MFC
pSysConReg->PCLK_GATE |= (1<<0); // MFC
pSysConReg->SCLK_GATE |= (1<<3); // MFC
}
return TRUE;
}
void *Phy2Vir_AddrMapping(unsigned int phy_addr, int mem_size)
{
#if 1
void *mappedAddr = NULL;
mappedAddr = DrvLib_MapIoSpace(phy_addr, mem_size, FALSE);
if (mappedAddr == NULL)
{
RETAILMSG(1, (L"[MFC:ERR] Phy2Vir_AddrMapping() : Mapping Failed [PA:0x%08x]\n\r", phy_addr));
}
return mappedAddr;
#else
BOOL b;
void *reserved_mem;
reserved_mem = (void *)VirtualAlloc(NULL, mem_size, MEM_RESERVE, PAGE_NOACCESS);
if (reserved_mem == NULL) {
ERRORMSG(1,(TEXT("For IOPreg: VirtualAlloc failed!\r\n")));
return 0;
}
b = VirtualCopy(reserved_mem,
(void *)(phy_addr >> 8),
mem_size,
PAGE_PHYSICAL | PAGE_READWRITE | PAGE_NOCACHE);
if (b == FALSE) {
VirtualFree(reserved_mem, 0, MEM_RELEASE);
return NULL;
}
return reserved_mem;
#endif
}
// 08.03.14 by KYS
// The function that initilize GPIO for DAT, CD and WP lines.
BOOL CSDHController::InitGPIO() {
volatile S3C6410_GPIO_REG *pIOPreg = NULL;
pIOPreg = (volatile S3C6410_GPIO_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_GPIO, sizeof(S3C6410_GPIO_REG), FALSE);
if (pIOPreg == NULL) {
RETAILMSG(1, (TEXT("[HSMMC1] GPIO registers is *NOT* mapped.\n")));
return FALSE;
}
RETAILMSG(_DBG_, (TEXT("[HSMMC1] Setting registers for the GPIO.\n")));
#ifdef _SMDK6410_CH1_8BIT_
pIOPreg->GPHCON0 = (pIOPreg->GPHCON0 & ~(0xFFFFFFFF)) | (0x22222222); // 4'b0010 for the MMC 1
pIOPreg->GPHCON1 = (pIOPreg->GPHCON1 &~(0xFF)) | (0x22); // 4'b0010 for the MMC 1
pIOPreg->GPHPUD &= ~(0xFFFFF); // Pull-up/down disabled
#else // DAT 4-Bit
pIOPreg->GPHCON0 = (pIOPreg->GPHCON0 & ~(0xFFFFFF)) | (0x222222); // 4'b0010 for the MMC 1
pIOPreg->GPHPUD &= ~(0xFFF); // Pull-up/down disabled
#endif
#ifdef _SMDK6410_CH1_WP_
pIOPreg->GPFCON &= ~(0x3<<26); // WP_SD1
pIOPreg->GPFPUD &= ~(0x3<<26); // Pull-up/down disabled
#endif
pIOPreg->GPGCON = (pIOPreg->GPGCON & ~(0xF<<24)) | (0x3<<24); // MMC CDn1
pIOPreg->GPGPUD &= ~(0x3<<12); // Pull-up/down disabled
DrvLib_UnmapIoSpace((PVOID)pIOPreg);
return TRUE;
}
BOOL CSerialPDD::Open()
{
PHYSICAL_ADDRESS ioPhysicalBase = { S3C6410_BASE_REG_PA_GPIO, 0};
ULONG inIoSpace = 0;
if (InterlockedExchange(&m_lOpenCount,1) !=0)
return FALSE;
PREFAST_ASSERT(m_PowerHelperHandle!=INVALID_HANDLE_VALUE);
ASSERT(m_hPowerLock==NULL);
m_hPowerLock= DDKPwr_RequestLevel( m_PowerHelperHandle, D0 );
ASSERT(m_hPowerLock!=NULL);
SetDefaultConfiguration();
InitLine(TRUE);
InitReceive(TRUE);
InitXmit(TRUE);
if(cUart_Index==3)
{
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
// Map it if it is Memeory Mapped IO.
g_pIOPregs = (S3C6410_GPIO_REG *)DrvLib_MapIoSpace(ioPhysicalBase.LowPart , sizeof(S3C6410_GPIO_REG),FALSE);
g_pIOPregs->GPCCON &= ~(0xf<<28); ///< Clear Bit
g_pIOPregs->GPCCON |= (0x1<<28); ///< Select UART IP
g_pIOPregs->GPCPUD &= ~(0x3<<14); ///< Pull-Up/Down Disable
//g_pIOPregs->GPCDAT |=1<<7;
}
}
return TRUE;
}
// 08.03.14 by KYS
// The function that initilize SYSCON for a clock gating.
BOOL CSDHController::InitClkPwr() {
volatile S3C6410_SYSCON_REG *pCLKPWR = NULL;
pCLKPWR = (volatile S3C6410_SYSCON_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_SYSCON, sizeof(S3C6410_SYSCON_REG), FALSE);
if (pCLKPWR == NULL) {
RETAILMSG(1, (TEXT("[HSMMC1] Clock & Power Management Special Register is *NOT* mapped.\n")));
return FALSE;
}
#ifdef _SRCCLK_48MHZ_
RETAILMSG(_DBG_, (TEXT("[HSMMC1] Setting registers for the USB48MHz (EXTCLK for SDCLK) : SYSCon.\n")));
// SCLK_HSMMC#_48 : CLK48M_PHY(OTH PHY 48MHz Clock Source from SYSCON block)
// To use the USB clock, must be set the "USB_SIG_MASK" bit in the syscon register.
pCLKPWR->OTHERS |= (0x1<<16); // set USB_SIG_MASK
pCLKPWR->HCLK_GATE |= (0x1<<18); // Gating HCLK for HSMMC1
pCLKPWR->SCLK_GATE |= (0x1<<28); // Gating special clock for HSMMC1 (SCLK_MMC1_48)
#else
RETAILMSG(_DBG_, (TEXT("[HSMMC1] Setting registers for the EPLL (for SDCLK) : SYSCon.\n")));
// SCLK_HSMMC# : EPLLout, MPLLout, PLL_source_clk or CLK27 clock
// (from SYSCON block, can be selected by MMC#_SEL[1:0] fields of the CLK_SRC register in SYSCON block)
// Set the clock source to EPLL out for CLKMMC1
pCLKPWR->CLK_SRC = (pCLKPWR->CLK_SRC & ~(0x3<<20) & ~(0x1<<2)) | // Control MUX(MMC1:MOUT EPLL)
(0x1<<2); // Control MUX(EPLL:FOUT EPLL)
pCLKPWR->HCLK_GATE |= (0x1<<18); // Gating HCLK for HSMMC1
pCLKPWR->SCLK_GATE = (pCLKPWR->SCLK_GATE & ~(0x3F<<24)) | (0x1<<25); // Gating special clock for HSMMC1 (SCLK_MMC1)
#endif
DrvLib_UnmapIoSpace((PVOID)pCLKPWR);
return TRUE;
}
// 08.03.14 by KYS
// The function that initilize the register for HSMMC Control.
BOOL CSDHController::InitHSMMC() {
volatile S3C6410_HSMMC_REG *pHSMMC = NULL;
pHSMMC = (volatile S3C6410_HSMMC_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_HSMMC1, sizeof(S3C6410_HSMMC_REG), FALSE);
if (pHSMMC == NULL) {
RETAILMSG(1, (TEXT("[HSMMC1] HSMMC Special Register is *NOT* mapped.\n")));
return FALSE;
}
#ifdef _SRCCLK_48MHZ_
RETAILMSG(_DBG_, (TEXT("[HSMMC1] Setting registers for the USB48MHz (EXTCLK) : HSMMCCon.\n")));
// Set the clock source to USB_PHY for CLKMMC1
pHSMMC->CONTROL2 = (pHSMMC->CONTROL2 & ~(0xffffffff)) |
(0x3<<9) | // Debounce Filter Count 0x3=64 iSDCLK
(0x1<<8) | // SDCLK Hold Enable
(0x3<<4); // Base Clock Source = External Clock
#else
RETAILMSG(_DBG_, (TEXT("[HSMMC1] Setting registers for the EPLL : HSMMCCon.\n")));
// Set the clock source to EPLL out for CLKMMC1
pHSMMC->CONTROL2 = (pHSMMC->CONTROL2 & ~(0xffffffff)) |
(0x3<<9) | // Debounce Filter Count 0x3=64 iSDCLK
(0x1<<8) | // SDCLK Hold Enable
(0x2<<4); // Base Clock Source = EPLL out
#endif
DrvLib_UnmapIoSpace((PVOID)pHSMMC);
return TRUE;
}
// 08.03.14 by KYS
// The function that initilize GPIO for DAT, CD and WP lines.
BOOL CSDHController::InitGPIO() {
volatile S3C6410_GPIO_REG *pIOPreg = NULL;
pIOPreg = (volatile S3C6410_GPIO_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_GPIO, sizeof(S3C6410_GPIO_REG), FALSE);
if (pIOPreg == NULL) {
RETAILMSG(1, (TEXT("[HSMMC0] GPIO registers is *NOT* mapped.\n")));
return FALSE;
}
RETAILMSG(_DBG_, (TEXT("[HSMMC0] Setting registers for the GPIO.\n")));
pIOPreg->GPGCON = (pIOPreg->GPGCON & ~(0xFFFFFF)) | (0x222222); // 4'b0010 for the MMC 0
pIOPreg->GPGPUD &= ~(0xFFF); // Pull-up/down disabled
#ifdef _SMDK6410_CH0_WP_
pIOPreg->GPNCON &= ~(0x3<<24); // WP_SD0
pIOPreg->GPNPUD &= ~(0x3<<24); // Pull-up/down disabled
#endif
#ifndef _SMDK6410_CH0_EXTCD_
pIOPreg->GPGCON = (pIOPreg->GPGCON & ~(0xF<<24)) | (0x2<<24); // SD CD0
pIOPreg->GPGPUD &= ~(0x3<<12); // Pull-up/down disabled
#endif
#ifdef _SMDK6410_CH0_EXTCD_
// 08.03.22 by KYS
// Setting for card detect pin of HSMMC ch0 on SMDK6410.
pIOPreg->GPNCON = ( pIOPreg->GPNCON & ~(0x3<<26) ) | (0x2<<26); // SD_CD0 by EINT13
pIOPreg->GPNPUD = ( pIOPreg->GPNPUD & ~(0x3<<26) ) | (0x0<<26); // pull-up/down disabled
pIOPreg->EINT0CON0 = ( pIOPreg->EINT0CON0 & ~(0x7<<24)) | (0x7<<24); // Both edge triggered
pIOPreg->EINT0PEND = ( pIOPreg->EINT0PEND | (0x1<<13) ); //clear EINT19 pending bit
pIOPreg->EINT0MASK = ( pIOPreg->EINT0MASK & ~(0x1<<13)); //enable EINT19
#endif
DrvLib_UnmapIoSpace((PVOID)pIOPreg);
return TRUE;
}
virtual BOOL Init()
{
PHYSICAL_ADDRESS ioPhysicalBase = { S3C6400_BASE_REG_PA_GPIO, 0};
ULONG inIoSpace = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
// Map it if it is Memeory Mapped IO.
m_pIOPregs =(S3C6400_GPIO_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart, sizeof(S3C6400_GPIO_REG),FALSE);
}
ioPhysicalBase.LowPart = S3C6400_BASE_REG_PA_SYSCON;
ioPhysicalBase.HighPart = 0;
if (TranslateBusAddr(m_hParent,Internal,0, ioPhysicalBase,&inIoSpace,&ioPhysicalBase))
{
m_pSysconRegs = (S3C6400_SYSCON_REG *) DrvLib_MapIoSpace(ioPhysicalBase.LowPart,sizeof(S3C6400_SYSCON_REG),FALSE);
}
if(m_pSysconRegs)
{
m_pSysconRegs->PCLK_GATE |= (1<<4); // UART3
m_pSysconRegs->SCLK_GATE |= (1<<5); // UART0~3
}
if (m_pIOPregs)
{
DDKISRINFO ddi;
if (GetIsrInfo(&ddi)== ERROR_SUCCESS &&
KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &ddi.dwIrq, sizeof(UINT32), &ddi.dwSysintr, sizeof(UINT32), NULL))
{
//RETAILMSG( TRUE, (TEXT("DEBUG: Serial3 SYSINTR : %d\r\n"), (PBYTE)&ddi.dwSysintr));
RegSetValueEx(DEVLOAD_SYSINTR_VALNAME,REG_DWORD,(PBYTE)&ddi.dwSysintr, sizeof(UINT32));
}
else
{
return FALSE;
}
// TXD3(GPB3), RXD3(GPB2)
m_pIOPregs->GPBCON &= ~(0xf<<8 | 0xf<<12);
m_pIOPregs->GPBCON |= (0x2<<8 | 0x2<<12);
m_pIOPregs->GPBPUD &= ~(0x3<<4 | 0x3<<6);
return CPdd6400Uart::Init();
}
return FALSE;
}
// 08.03.22 by KYS
// New function for enabling the Card detect interrupt of HSMMC ch0 on SMDK6410.
BOOL CSDHController::EnableCardDetectInterrupt() {
volatile S3C6410_GPIO_REG *pIOPreg = NULL;
pIOPreg = (volatile S3C6410_GPIO_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_GPIO, sizeof(S3C6410_GPIO_REG), FALSE);
if (pIOPreg == NULL)
{
RETAILMSG (1,(TEXT("[HSMMC0] GPIO registers is *NOT* mapped.\n")));
return FALSE;
}
pIOPreg->EINT0PEND = ( pIOPreg->EINT0PEND | (0x1<<13)); //clear EINT13 pending bit
pIOPreg->EINT0MASK = ( pIOPreg->EINT0MASK & ~(0x1<<13)); //enable EINT13
DrvLib_UnmapIoSpace((PVOID)pIOPreg);
return TRUE;
}
/* InitializeOHCI
*
* Configure and initialize OHCI card
*
* Return Value:
* Return TRUE if card could be located and configured, otherwise FALSE
*/
static BOOL
InitializeOHCI(
SOhcdPdd * pPddObject, // IN - Pointer to PDD structure
LPCWSTR szDriverRegKey) // IN - Pointer to active registry key string
{
PUCHAR ioPortBase = NULL;
DWORD dwAddrLen;
DWORD dwIOSpace;
BOOL InstallIsr = FALSE;
BOOL fResult = FALSE;
LPVOID pobMem = NULL;
LPVOID pobOhcd = NULL;
DWORD PhysAddr;
DWORD dwHPPhysicalMemSize;
HKEY hKey=NULL;
DDKWINDOWINFO dwi;
DDKISRINFO dii;
USBH_MSG((_T("[USBH] ++InitializeOHCI()\n\r")));
g_pSysConReg = (S3C6410_SYSCON_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_SYSCON, sizeof(S3C6410_SYSCON_REG), FALSE);
if (g_pSysConReg == NULL)
{
USBH_ERR((_T("[USBH:ERR] InitializeOHCI() : DrvLib_MapIoSpace() Failed\n")));
return FALSE;
}
#ifdef USE_SRCCLK_EPLL
//-----------------------
// Initialize Clock
// ClkSrc = MOUT_EPLL (96MHz)
// Divide by 2 (96/2=48MHz)
// HCLK, SCLK gate pass
//-----------------------
g_pSysConReg->CLK_SRC = (g_pSysConReg->CLK_SRC & ~(0x3<<5)) | (0x1<<5); // UHOST_SEL : MoutEPLL
g_pSysConReg->CLK_DIV1 = (g_pSysConReg->CLK_DIV1 & ~(0xf<<20)) | (0x1<<20); // UHOST_RATIO : 96 MHz / (1+1) = 48 MHz
#else
//-----------------------
// Initialize Clock
// ClkSrc = USB_PHY(48MHz)
// Divide by 1 (48/1=48MHz)
// HCLK, SCLK gate pass
//-----------------------
g_pSysConReg->OTHERS |= (1<<16); // Set SUB Signal Mask
g_pSysConReg->CLK_SRC &= ~(0x3<<5); // UHOST_SEL : 48MHz
g_pSysConReg->CLK_DIV1 &= ~(0xf<<20); // UHOST_RATIO : 48 MHz / (0+1) = 48 MHz
#endif
g_pSysConReg->HCLK_GATE |= (0x1<<29); // HCLK_UHOST Pass (EVT1)
g_pSysConReg->SCLK_GATE |= (0x1<<30); // SCLK_UHOST Pass
if (RegOpenKeyEx(HKEY_LOCAL_MACHINE,szDriverRegKey,0,0,&hKey)!= ERROR_SUCCESS)
{
DEBUGMSG(ZONE_ERROR,(TEXT("InitializeOHCI:GetRegistryConfig RegOpenKeyEx(%s) failed\r\n"), szDriverRegKey));
return FALSE;
}
dwi.cbSize=sizeof(dwi);
dii.cbSize=sizeof(dii);
if ( (DDKReg_GetWindowInfo(hKey, &dwi ) != ERROR_SUCCESS)
|| (DDKReg_GetIsrInfo (hKey, &dii ) != ERROR_SUCCESS))
{
DEBUGMSG(ZONE_ERROR,(TEXT("InitializeOHCI:DDKReg_GetWindowInfo or DDKReg_GetWindowInfo failed\r\n")));
goto InitializeOHCI_Error;
}
if (dwi.dwNumMemWindows!=0)
{
PhysAddr = dwi.memWindows[0].dwBase;
dwAddrLen= dwi.memWindows[0].dwLen;
dwIOSpace = 0;
}
else if (dwi.dwNumIoWindows!=0)
{
PhysAddr= dwi.ioWindows[0].dwBase;
dwAddrLen = dwi.ioWindows[0].dwLen;
dwIOSpace = 1;
}
else
{
goto InitializeOHCI_Error;
}
DEBUGMSG(ZONE_INIT,(TEXT("OHCD: Read config from registry: Base Address: 0x%X, Length: 0x%X, I/O Port: %s, SysIntr: 0x%X, Interface Type: %u, Bus Number: %u\r\n"),
PhysAddr, dwAddrLen, dwIOSpace ? L"YES" : L"NO", dii.dwSysintr, dwi.dwInterfaceType, dwi.dwBusNumber));
ioPortBase = (PBYTE) PhysAddr;
if (!(fResult = ConfigureOHCICard(pPddObject, &ioPortBase, dwAddrLen, dwIOSpace,(INTERFACE_TYPE)dwi.dwInterfaceType, dwi.dwBusNumber)))
{
goto InitializeOHCI_Error;
}
if (dii.szIsrDll[0] != 0 && dii.szIsrHandler[0]!=0 && dii.dwIrq<0xff && dii.dwIrq>0 )
{
// Install ISR handler
pPddObject->IsrHandle = LoadIntChainHandler(dii.szIsrDll, dii.szIsrHandler, (BYTE)dii.dwIrq);
if (!pPddObject->IsrHandle)
{
DEBUGMSG(ZONE_ERROR, (L"OHCD: Couldn't install ISR handler\r\n"));
}
else
{
GIISR_INFO Info;
PHYSICAL_ADDRESS PortAddress = {PhysAddr, 0};
DEBUGMSG(ZONE_INIT, (L"OHCD: Installed ISR handler, Dll = '%s', Handler = '%s', Irq = %d\r\n",
dii.szIsrDll, dii.szIsrHandler, dii.dwIrq));
if (!BusTransBusAddrToStatic(pPddObject->hParentBusHandle,(INTERFACE_TYPE)dwi.dwInterfaceType, dwi.dwBusNumber, PortAddress, dwAddrLen, &dwIOSpace, (PPVOID)&PhysAddr))
{
DEBUGMSG(ZONE_ERROR, (L"OHCD: Failed TransBusAddrToStatic\r\n"));
goto InitializeOHCI_Error;
}
// Set up ISR handler
Info.SysIntr = dii.dwSysintr;
Info.CheckPort = TRUE;
Info.PortIsIO = (dwIOSpace) ? TRUE : FALSE;
Info.UseMaskReg = TRUE;
Info.PortAddr = PhysAddr + 0x0C;
Info.PortSize = sizeof(DWORD);
Info.MaskAddr = PhysAddr + 0x10;
if (!KernelLibIoControl(pPddObject->IsrHandle, IOCTL_GIISR_INFO, &Info, sizeof(Info), NULL, 0, NULL))
{
DEBUGMSG(ZONE_ERROR, (L"OHCD: KernelLibIoControl call failed.\r\n"));
}
}
}
// The PDD can supply a buffer of contiguous physical memory here, or can let the
// MDD try to allocate the memory from system RAM. We will use the HalAllocateCommonBuffer()
// API to allocate the memory and bus controller physical addresses and pass this information
// into the MDD.
if (GetRegistryPhysicalMemSize(szDriverRegKey,&pPddObject->dwPhysicalMemSize))
{
// A quarter for High priority Memory.
dwHPPhysicalMemSize = pPddObject->dwPhysicalMemSize/4;
// Align with page size.
pPddObject->dwPhysicalMemSize = (pPddObject->dwPhysicalMemSize + PAGE_SIZE -1) & ~(PAGE_SIZE -1);
dwHPPhysicalMemSize = ((dwHPPhysicalMemSize + PAGE_SIZE -1) & ~(PAGE_SIZE -1));
}
else
{
pPddObject->dwPhysicalMemSize=0;
dwHPPhysicalMemSize = 0 ;
}
if (pPddObject->dwPhysicalMemSize<gcTotalAvailablePhysicalMemory)
{
// Setup Minimun requirement.
pPddObject->dwPhysicalMemSize = gcTotalAvailablePhysicalMemory;
dwHPPhysicalMemSize = gcHighPriorityPhysicalMemory;
}
pPddObject->AdapterObject.ObjectSize = sizeof(DMA_ADAPTER_OBJECT);
pPddObject->AdapterObject.InterfaceType = dwi.dwInterfaceType;
pPddObject->AdapterObject.BusNumber = dwi.dwBusNumber;
if ((pPddObject->pvVirtualAddress = HalAllocateCommonBuffer(&pPddObject->AdapterObject, pPddObject->dwPhysicalMemSize, &pPddObject->LogicalAddress, FALSE)) == NULL)
{
goto InitializeOHCI_Error;
}
if (!(pobMem = HcdMdd_CreateMemoryObject(pPddObject->dwPhysicalMemSize, dwHPPhysicalMemSize, (PUCHAR) pPddObject->pvVirtualAddress, (PUCHAR) pPddObject->LogicalAddress.LowPart)))
{
goto InitializeOHCI_Error;
}
if (!(pobOhcd = HcdMdd_CreateHcdObject(pPddObject, pobMem, szDriverRegKey, ioPortBase, dii.dwSysintr)))
{
goto InitializeOHCI_Error;
}
pPddObject->lpvMemoryObject = pobMem;
pPddObject->lpvOhcdMddObject = pobOhcd;
_tcsncpy(pPddObject->szDriverRegKey, szDriverRegKey, MAX_PATH);
pPddObject->ioPortBase = ioPortBase;
pPddObject->dwSysIntr = dii.dwSysintr;
// PCI OHCI support suspend and resume
if ( hKey!=NULL)
{
DWORD dwCapability;
DWORD dwType;
DWORD dwLength = sizeof(DWORD);
if (RegQueryValueEx(hKey, HCD_CAPABILITY_VALNAME, 0, &dwType, (PUCHAR)&dwCapability, &dwLength) == ERROR_SUCCESS)
{
HcdMdd_SetCapability(pobOhcd, dwCapability);
USBH_INF((_T("[USBH:INF] InitializeOHCI() : USB Host Cap : 0x%08x\n"), dwCapability));
}
RegCloseKey(hKey);
}
USBH_MSG((_T("[USBH] --InitializeOHCI() : Success\n\r")));
return TRUE;
InitializeOHCI_Error:
if (g_pSysConReg != NULL)
{
DrvLib_UnmapIoSpace((PVOID)g_pSysConReg);
g_pSysConReg = NULL;
}
if (pPddObject->IsrHandle)
{
FreeIntChainHandler(pPddObject->IsrHandle);
pPddObject->IsrHandle = NULL;
}
if (pobOhcd)
{
HcdMdd_DestroyHcdObject(pobOhcd);
}
if (pobMem)
{
HcdMdd_DestroyMemoryObject(pobMem);
}
if(pPddObject->pvVirtualAddress)
{
HalFreeCommonBuffer(&pPddObject->AdapterObject, pPddObject->dwPhysicalMemSize, pPddObject->LogicalAddress, pPddObject->pvVirtualAddress, FALSE);
}
pPddObject->lpvMemoryObject = NULL;
pPddObject->lpvOhcdMddObject = NULL;
pPddObject->pvVirtualAddress = NULL;
if ( hKey!=NULL)
{
RegCloseKey(hKey);
}
USBH_ERR((_T("[USBH:ERR] --InitializeOHCI() : Error\n\r")));
return FALSE;
}
static BOOL
PWR_AllocResources(void)
{
DWORD dwIRQ;
PWRBTN_MSG((_T("[PWR] ++PWR_AllocResources()\r\n")));
//------------------
// GPIO Controller SFR
//------------------
g_pGPIOReg = (S3C6410_GPIO_REG *)DrvLib_MapIoSpace(S3C6410_BASE_REG_PA_GPIO, sizeof(S3C6410_GPIO_REG), FALSE);
if (g_pGPIOReg == NULL)
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : pGPIOReg DrvLib_MapIoSpace() Failed \n\r")));
return FALSE;
}
//--------------------
// Power Button Interrupt
//--------------------
dwIRQ = IRQ_EINT11;
g_dwSysIntrPowerBtn = SYSINTR_UNDEFINED;
g_hEventPowerBtn = NULL;
if (!KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &dwIRQ, sizeof(DWORD), &g_dwSysIntrPowerBtn, sizeof(DWORD), NULL))
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : IOCTL_HAL_REQUEST_SYSINTR Power Button Failed \n\r")));
g_dwSysIntrPowerBtn = SYSINTR_UNDEFINED;
return FALSE;
}
g_hEventPowerBtn = CreateEvent(NULL, FALSE, FALSE, NULL);
if(NULL == g_hEventPowerBtn)
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : CreateEvent() Power Button Failed \n\r")));
return FALSE;
}
if (!(InterruptInitialize(g_dwSysIntrPowerBtn, g_hEventPowerBtn, 0, 0)))
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : InterruptInitialize() Power Button Failed \n\r")));
return FALSE;
}
//--------------------
// Reset Button Interrupt
//--------------------
/*dwIRQ = IRQ_EINT9;
g_dwSysIntrResetBtn = SYSINTR_UNDEFINED;
g_hEventResetBtn = NULL;
if (!KernelIoControl(IOCTL_HAL_REQUEST_SYSINTR, &dwIRQ, sizeof(DWORD), &g_dwSysIntrResetBtn, sizeof(DWORD), NULL))
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : IOCTL_HAL_REQUEST_SYSINTR Reset Button Failed \n\r")));
g_dwSysIntrResetBtn = SYSINTR_UNDEFINED;
return FALSE;
}
g_hEventResetBtn = CreateEvent(NULL, FALSE, FALSE, NULL);
if(NULL == g_hEventResetBtn)
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : CreateEvent() Reset Button Failed \n\r")));
return FALSE;
}
if (!(InterruptInitialize(g_dwSysIntrResetBtn, g_hEventResetBtn, 0, 0)))
{
PWRBTN_ERR((_T("[PWR:ERR] PWR_AllocResources() : InterruptInitialize() Reset Button Failed \n\r")));
return FALSE;
}
*/
PWRBTN_MSG((_T("[PWR] --PWR_AllocResources()\r\n")));
return TRUE;
}