static void I2C_MasterTransferEDMAConfig(I2C_Type *base, i2c_master_edma_handle_t *handle)
{
edma_transfer_config_t transfer_config;
if (handle->transfer.direction == kI2C_Read)
{
transfer_config.srcAddr = (uint32_t)I2C_GetDataRegAddr(base);
transfer_config.destAddr = (uint32_t)(handle->transfer.data);
transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
transfer_config.srcOffset = 0;
transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
transfer_config.destOffset = 1;
transfer_config.minorLoopBytes = 1;
}
else
{
transfer_config.srcAddr = (uint32_t)(handle->transfer.data + 1);
transfer_config.destAddr = (uint32_t)I2C_GetDataRegAddr(base);
transfer_config.majorLoopCounts = (handle->transfer.dataSize - 1);
transfer_config.srcTransferSize = kEDMA_TransferSize1Bytes;
transfer_config.srcOffset = 1;
transfer_config.destTransferSize = kEDMA_TransferSize1Bytes;
transfer_config.destOffset = 0;
transfer_config.minorLoopBytes = 1;
}
EDMA_SubmitTransfer(handle->dmaHandle, &transfer_config);
EDMA_StartTransfer(handle->dmaHandle);
}
status_t FLEXIO_CAMERA_TransferReceiveEDMA(FLEXIO_CAMERA_Type *base,
flexio_camera_edma_handle_t *handle,
flexio_camera_transfer_t *xfer)
{
assert(handle->rxEdmaHandle);
edma_transfer_config_t xferConfig;
status_t status;
/* If previous RX not finished. */
if (kFLEXIO_CAMERA_RxBusy == handle->rxState)
{
status = kStatus_FLEXIO_CAMERA_RxBusy;
}
else
{
handle->rxState = kFLEXIO_CAMERA_RxBusy;
/* Prepare transfer. */
EDMA_PrepareTransfer(&xferConfig, (void *)FLEXIO_CAMERA_GetRxBufferAddress(base), 32, (void *)xfer->dataAddress,
32, 32, xfer->dataNum, kEDMA_PeripheralToMemory);
/* Submit transfer. */
EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
EDMA_StartTransfer(handle->rxEdmaHandle);
/* Enable CAMERA RX EDMA. */
FLEXIO_CAMERA_EnableRxDMA(base, true);
status = kStatus_Success;
}
return status;
}
/*!
* brief Performs a non-blocking SPDIF receive using eDMA.
*
* note This interface returns immediately after the transfer initiates. Call
* the SPDIF_GetReceiveRemainingBytes to poll the transfer status and check whether the SPDIF transfer is finished.
*
* param base SPDIF base pointer
* param handle SPDIF eDMA handle pointer.
* param xfer Pointer to DMA transfer structure.
* retval kStatus_Success Start a SPDIF eDMA receive successfully.
* retval kStatus_InvalidArgument The input argument is invalid.
* retval kStatus_RxBusy SPDIF is busy receiving data.
*/
status_t SPDIF_TransferReceiveEDMA(SPDIF_Type *base, spdif_edma_handle_t *handle, spdif_edma_transfer_t *xfer)
{
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t srcAddr = SPDIF_RxGetLeftDataRegisterAddress(base);
/* Check if input parameter invalid */
if ((xfer->leftData == NULL) || (xfer->dataSize == 0U) || (xfer->rightData == NULL))
{
return kStatus_InvalidArgument;
}
if ((handle->spdifQueue[handle->queueUser].leftData) || (handle->spdifQueue[handle->queueUser].rightData))
{
return kStatus_SPDIF_QueueFull;
}
/* Change the state of handle */
handle->state = kSPDIF_Busy;
/* Update the queue state */
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->spdifQueue[handle->queueUser].leftData = xfer->leftData;
handle->spdifQueue[handle->queueUser].dataSize = xfer->dataSize;
handle->spdifQueue[handle->queueUser].rightData = xfer->rightData;
handle->queueUser = (handle->queueUser + 1) % SPDIF_XFER_QUEUE_SIZE;
/* Store the initially configured eDMA minor byte transfer count into the SPDIF handle */
handle->nbytes = handle->count * 8U;
/* Prepare edma configure */
EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->leftData, 4U, handle->count * 4U, xfer->dataSize,
kEDMA_PeripheralToMemory);
/* Use specific submit function to enable channel link */
SPDIF_SubmitTransfer(handle->dmaLeftHandle, &config, handle->dmaRightHandle->channel);
/* Prepare right channel */
srcAddr = SPDIF_RxGetRightDataRegisterAddress(base);
EDMA_PrepareTransfer(&config, (void *)srcAddr, 4U, xfer->rightData, 4U, handle->count * 4U, xfer->dataSize,
kEDMA_PeripheralToMemory);
EDMA_SubmitTransfer(handle->dmaRightHandle, &config);
/* Start DMA transfer */
EDMA_StartTransfer(handle->dmaLeftHandle);
EDMA_StartTransfer(handle->dmaRightHandle);
/* Enable DMA enable bit */
SPDIF_EnableDMA(base, kSPDIF_RxDMAEnable, true);
/* Enable SPDIF Rx clock */
SPDIF_RxEnable(base, true);
return kStatus_Success;
}
status_t SAI_TransferReceiveEDMA(I2S_Type *base, sai_edma_handle_t *handle, sai_transfer_t *xfer)
{
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t srcAddr = SAI_RxGetDataRegisterAddress(base, handle->channel);
/* Check if input parameter invalid */
if ((xfer->data == NULL) || (xfer->dataSize == 0U))
{
return kStatus_InvalidArgument;
}
if (handle->saiQueue[handle->queueUser].data)
{
return kStatus_SAI_QueueFull;
}
/* Change the state of handle */
handle->state = kSAI_Busy;
/* Update queue state */
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->saiQueue[handle->queueUser].data = xfer->data;
handle->saiQueue[handle->queueUser].dataSize = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % SAI_XFER_QUEUE_SIZE;
/* Prepare edma configure */
EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
handle->count * handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory);
/* Store the initially configured eDMA minor byte transfer count into the SAI handle */
handle->nbytes = handle->count * handle->bytesPerFrame;
EDMA_SubmitTransfer(handle->dmaHandle, &config);
/* Start DMA transfer */
EDMA_StartTransfer(handle->dmaHandle);
/* Enable DMA enable bit */
SAI_RxEnableDMA(base, kSAI_FIFORequestDMAEnable, true);
/* Enable the channel FIFO */
base->RCR3 |= I2S_RCR3_RCE(1U << handle->channel);
/* Enable SAI Rx clock */
SAI_RxEnable(base, true);
return kStatus_Success;
}
status_t FLEXIO_I2S_TransferReceiveEDMA(FLEXIO_I2S_Type *base,
flexio_i2s_edma_handle_t *handle,
flexio_i2s_transfer_t *xfer)
{
assert(handle && xfer);
edma_transfer_config_t config = {0};
uint32_t srcAddr = FLEXIO_I2S_RxGetDataRegisterAddress(base) + (4U - handle->bytesPerFrame);
/* Check if input parameter invalid */
if ((xfer->data == NULL) || (xfer->dataSize == 0U))
{
return kStatus_InvalidArgument;
}
if (handle->queue[handle->queueUser].data)
{
return kStatus_FLEXIO_I2S_QueueFull;
}
/* Change the state of handle */
handle->state = kFLEXIO_I2S_Busy;
/* Update queue state */
handle->queue[handle->queueUser].data = xfer->data;
handle->queue[handle->queueUser].dataSize = xfer->dataSize;
handle->transferSize[handle->queueUser] = xfer->dataSize;
handle->queueUser = (handle->queueUser + 1) % FLEXIO_I2S_XFER_QUEUE_SIZE;
/* Prepare edma configure */
EDMA_PrepareTransfer(&config, (void *)srcAddr, handle->bytesPerFrame, xfer->data, handle->bytesPerFrame,
handle->bytesPerFrame, xfer->dataSize, kEDMA_PeripheralToMemory);
/* Store the initially configured eDMA minor byte transfer count into the FLEXIO I2S handle */
handle->nbytes = handle->bytesPerFrame;
EDMA_SubmitTransfer(handle->dmaHandle, &config);
/* Start DMA transfer */
EDMA_StartTransfer(handle->dmaHandle);
/* Enable DMA enable bit */
FLEXIO_I2S_RxEnableDMA(base, true);
/* Enable FLEXIO I2S Rx clock */
FLEXIO_I2S_Enable(base, true);
return kStatus_Success;
}
status_t LPUART_ReceiveEDMA(LPUART_Type *base, lpuart_edma_handle_t *handle, lpuart_transfer_t *xfer)
{
assert(handle);
assert(handle->rxEdmaHandle);
assert(xfer);
assert(xfer->data);
assert(xfer->dataSize);
edma_transfer_config_t xferConfig;
status_t status;
/* If previous RX not finished. */
if (kLPUART_RxBusy == handle->rxState)
{
status = kStatus_LPUART_RxBusy;
}
else
{
handle->rxState = kLPUART_RxBusy;
handle->rxDataSizeAll = xfer->dataSize;
/* Prepare transfer. */
EDMA_PrepareTransfer(&xferConfig, (void *)LPUART_GetDataRegisterAddress(base), sizeof(uint8_t), xfer->data,
sizeof(uint8_t), sizeof(uint8_t), xfer->dataSize, kEDMA_PeripheralToMemory);
/* Store the initially configured eDMA minor byte transfer count into the LPUART handle */
handle->nbytes = sizeof(uint8_t);
/* Submit transfer. */
EDMA_SubmitTransfer(handle->rxEdmaHandle, &xferConfig);
EDMA_StartTransfer(handle->rxEdmaHandle);
/* Enable LPUART RX EDMA. */
LPUART_EnableRxDMA(base, true);
status = kStatus_Success;
}
return status;
}
/*!
* @brief Main function
*/
int main(void)
{
uint32_t srcAddr[BUFFER_LENGTH] = {0x01U, 0x02U, 0x03U, 0x04U, 0x05U, 0x06U, 0x07U, 0x08U};
uint32_t destAddr[BUFFER_LENGTH] = {0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U};
uint32_t i = 0;
edma_transfer_config_t transferConfig;
edma_tcd_t *tcdMemoryPoolPtr;
edma_config_t userConfig;
BOARD_InitPins();
BOARD_BootClockRUN();
BOARD_InitDebugConsole();
/* Print source buffer */
PRINTF("EDMA memory to memory transfer example begin.\r\n\r\n");
PRINTF("Destination Buffer:\r\n");
for (i = 0; i < BUFFER_LENGTH; i++)
{
PRINTF("%d\t", destAddr[i]);
}
/* Configure DMAMUX */
DMAMUX_Init(DMAMUX0);
DMAMUX_SetSource(DMAMUX0, 0, 63);
DMAMUX_EnableChannel(DMAMUX0, 0);
/* Configure EDMA one shot transfer */
/*
* userConfig.enableRoundRobinArbitration = false;
* userConfig.enableHaltOnError = true;
* userConfig.enableContinuousLinkMode = false;
* userConfig.enableDebugMode = false;
*/
EDMA_GetDefaultConfig(&userConfig);
EDMA_Init(DMA0, &userConfig);
EDMA_CreateHandle(&g_EDMA_Handle, DMA0, 0);
EDMA_SetCallback(&g_EDMA_Handle, EDMA_Callback, NULL);
EDMA_ResetChannel(g_EDMA_Handle.base, g_EDMA_Handle.channel);
/* Allocate TCD memory poll */
tcdMemoryPoolPtr = (edma_tcd_t *)malloc(sizeof(edma_tcd_t) * (TCD_QUEUE_SIZE + 1));
if (tcdMemoryPoolPtr != NULL)
{
tcdMemoryPoolPtr = (edma_tcd_t *)((uint32_t)(tcdMemoryPoolPtr + 1) & (~0x1FU));
EDMA_InstallTCDMemory(&g_EDMA_Handle, tcdMemoryPoolPtr, TCD_QUEUE_SIZE);
/* Configure and submit transfer structure 1 */
EDMA_PrepareTransfer(&transferConfig, srcAddr, sizeof(srcAddr[0]), destAddr, sizeof(destAddr[0]),
sizeof(srcAddr[0]), sizeof(srcAddr[0]) * HALF_BUFFER_LENGTH, kEDMA_MemoryToMemory);
EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig);
/* Configure and submit transfer structure 2 */
EDMA_PrepareTransfer(&transferConfig, &srcAddr[4], sizeof(srcAddr[0]), &destAddr[4], sizeof(destAddr[0]),
sizeof(srcAddr[0]), sizeof(srcAddr[0]) * HALF_BUFFER_LENGTH, kEDMA_MemoryToMemory);
EDMA_SubmitTransfer(&g_EDMA_Handle, &transferConfig);
}
EDMA_StartTransfer(&g_EDMA_Handle);
/* Wait for EDMA transfer finish */
while (g_Transfer_Done != true)
{
}
/* Print destination buffer */
PRINTF("\r\n\r\nEDMA memory to memory transfer example finish.\r\n\r\n");
PRINTF("Destination Buffer:\r\n");
for (i = 0; i < BUFFER_LENGTH; i++)
{
PRINTF("%d\t", destAddr[i]);
}
while (1)
{
}
}
static void FLEXIO_SPI_EDMAConfig(FLEXIO_SPI_Type *base,
flexio_spi_master_edma_handle_t *handle,
flexio_spi_transfer_t *xfer)
{
edma_transfer_config_t xferConfig;
flexio_spi_shift_direction_t direction;
uint8_t bytesPerFrame;
/* Configure the values in handle. */
switch (xfer->flags)
{
case kFLEXIO_SPI_8bitMsb:
bytesPerFrame = 1;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_8bitLsb:
bytesPerFrame = 1;
direction = kFLEXIO_SPI_LsbFirst;
break;
case kFLEXIO_SPI_16bitMsb:
bytesPerFrame = 2;
direction = kFLEXIO_SPI_MsbFirst;
break;
case kFLEXIO_SPI_16bitLsb:
bytesPerFrame = 2;
direction = kFLEXIO_SPI_LsbFirst;
break;
default:
bytesPerFrame = 1U;
direction = kFLEXIO_SPI_MsbFirst;
assert(true);
break;
}
/* Save total transfer size. */
handle->transferSize = xfer->dataSize;
/* Configure tx transfer EDMA. */
xferConfig.destAddr = FLEXIO_SPI_GetTxDataRegisterAddress(base, direction);
xferConfig.destOffset = 0;
if (bytesPerFrame == 1U)
{
xferConfig.srcTransferSize = kEDMA_TransferSize1Bytes;
xferConfig.destTransferSize = kEDMA_TransferSize1Bytes;
xferConfig.minorLoopBytes = 1;
}
else
{
if (direction == kFLEXIO_SPI_MsbFirst)
{
xferConfig.destAddr -= 1U;
}
xferConfig.srcTransferSize = kEDMA_TransferSize2Bytes;
xferConfig.destTransferSize = kEDMA_TransferSize2Bytes;
xferConfig.minorLoopBytes = 2;
}
/* Configure DMA channel. */
if (xfer->txData)
{
xferConfig.srcOffset = bytesPerFrame;
xferConfig.srcAddr = (uint32_t)(xfer->txData);
}
else
{
/* Disable the source increasement and source set to dummyData. */
xferConfig.srcOffset = 0;
xferConfig.srcAddr = (uint32_t)(&s_dummyData);
}
xferConfig.majorLoopCounts = (xfer->dataSize / xferConfig.minorLoopBytes);
/* Store the initially configured eDMA minor byte transfer count into the FLEXIO SPI handle */
handle->nbytes = xferConfig.minorLoopBytes;
if (handle->txHandle)
{
EDMA_SubmitTransfer(handle->txHandle, &xferConfig);
}
/* Configure tx transfer EDMA. */
if (xfer->rxData)
{
xferConfig.srcAddr = FLEXIO_SPI_GetRxDataRegisterAddress(base, direction);
if (bytesPerFrame == 2U)
{
if (direction == kFLEXIO_SPI_LsbFirst)
{
xferConfig.srcAddr -= 1U;
}
}
xferConfig.srcOffset = 0;
xferConfig.destAddr = (uint32_t)(xfer->rxData);
xferConfig.destOffset = bytesPerFrame;
EDMA_SubmitTransfer(handle->rxHandle, &xferConfig);
handle->rxInProgress = true;
FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_RxDmaEnable, true);
EDMA_StartTransfer(handle->rxHandle);
}
/* Always start Tx transfer. */
if (handle->txHandle)
{
handle->txInProgress = true;
FLEXIO_SPI_EnableDMA(base, kFLEXIO_SPI_TxDmaEnable, true);
EDMA_StartTransfer(handle->txHandle);
}
}