//*****************************************************************************
//
// Configures all pins associated with the Extended Peripheral Interface (EPI).
//
// \param eDaughter identifies the attached daughter board (if any).
//
// This function configures all pins forming part of the EPI on the device and
// configures the EPI peripheral appropriately for whichever hardware we
// detect is connected to it. On exit, the EPI peripheral is enabled and all
// pins associated with the interface are configured as EPI signals. Drive
// strength is set to 8mA.
//
//*****************************************************************************
static void
EPIPinConfigSet(tDaughterIDInfo *psInfo)
{
unsigned long ulLoop, ulClk, ulNsPerTick, ulRefresh;
unsigned char pucPins[NUM_GPIO_PORTS];
//
// Enable the EPI peripheral
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// Clear our pin bit mask array.
//
for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
{
pucPins[ulLoop] = 0;
}
//
// Determine the pin bit masks for the EPI pins for each GPIO port.
//
for(ulLoop = 0; ulLoop < NUM_EPI_SIGNALS; ulLoop++)
{
//
// Is this EPI signal required?
//
if(psInfo->ulEPIPins & (1 << ulLoop))
{
//
// Yes - set the appropriate bit in our pin bit mask array.
//
pucPins[g_psEPIPinInfo[ulLoop].ucPortIndex] |=
(1 << g_psEPIPinInfo[ulLoop].ucPin);
}
}
//
// At this point, pucPins contains bit masks for each GPIO port with 1s in
// the positions of every required EPI signal. Now we need to configure
// those pins appropriately. Cycle through each port configuring EPI pins
// in any port which contains them.
//
for(ulLoop = 0; ulLoop < NUM_GPIO_PORTS; ulLoop++)
{
//
// Are there any EPI pins used in this port?
//
if(pucPins[ulLoop])
{
//
// Yes - configure the EPI pins.
//
GPIOPadConfigSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU);
GPIODirModeSet(g_pulGPIOBase[ulLoop], pucPins[ulLoop],
GPIO_DIR_MODE_HW);
}
}
//
// Now set the EPI operating mode for the daughter board detected. We need
// to determine some timing information based on the ID block we have and
// also the current system clock.
//
ulClk = SysCtlClockGet();
ulNsPerTick = 1000000000/ulClk;
//
// If the EPI is not disabled (the daughter board may, for example, want
// to use all the pins for GPIO), configure the interface as required.
//
if(psInfo->ucEPIMode != EPI_MODE_DISABLE)
{
//
// Set the EPI clock divider to ensure a basic EPI clock rate no faster
// than defined via the ucRate0nS and ucRate1nS fields in the info
// structure.
//
EPIDividerSet(EPI0_BASE, CalcEPIDivider(psInfo, ulNsPerTick));
//
// Set the basic EPI operating mode based on the value from the info
// structure.
//
EPIModeSet(EPI0_BASE, psInfo->ucEPIMode);
//
// Carry out mode-dependent configuration.
//
switch(psInfo->ucEPIMode)
{
//
// The daughter board must be configured for SDRAM operation.
//
case EPI_MODE_SDRAM:
{
//
// Work out the SDRAM configuration settings based on the
// supplied ID structure and system clock rate.
//
ulLoop = SDRAMConfigGet(psInfo, ulClk, &ulRefresh);
//
// Set the SDRAM configuration.
//
EPIConfigSDRAMSet(EPI0_BASE, ulLoop, ulRefresh);
break;
}
//
// The daughter board must be configured for HostBus8 operation.
//
case EPI_MODE_HB8:
{
//
// Determine the number of read and write wait states required
// to meet the supplied access timing.
//
ulLoop = HB8ConfigGet(psInfo);
//
// Set the HostBus8 configuration.
//
EPIConfigHB8Set(EPI0_BASE, ulLoop, psInfo->ucMaxWait);
break;
}
//
// The daughter board must be configured for Non-Moded/General
// Purpose operation.
//
case EPI_MODE_GENERAL:
{
EPIConfigGPModeSet(EPI0_BASE, psInfo->ulConfigFlags,
psInfo->ucFrameCount, psInfo->ucMaxWait);
break;
}
}
//
// Set the EPI address mapping.
//
EPIAddressMapSet(EPI0_BASE, psInfo->ucAddrMap);
}
}
//*****************************************************************************
//
// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
// simple C array. This example shows how to read and write to an SDRAM card
// using the EPI bus in SDRAM mode.
//
//*****************************************************************************
int
main(void)
{
uint32_t ui32Val, ui32Freq, ui32SysClock;
//
// Set the clocking to run at 120MHz from the PLL.
// TODO: Update this call to set the system clock frequency your
// application requires.
//
ui32SysClock = SysCtlClockFreqSet((SYSCTL_OSC_INT | SYSCTL_USE_PLL |
SYSCTL_CFG_VCO_320), 120000000);
//
// Set up the serial console to use for displaying messages. This is
// just for this example program and is not needed for EPI operation.
//
InitConsole();
//
// Display the setup on the console.
//
UARTprintf("EPI SDRAM Mode ->\n");
UARTprintf(" Type: SDRAM\n");
UARTprintf(" Starting Address: 0x%08x\n", SDRAM_MAPPING_ADDRESS);
UARTprintf(" End Address: 0x%08x\n",
(SDRAM_MAPPING_ADDRESS + SDRAM_END_ADDRESS));
UARTprintf(" Data: 16-bit\n");
UARTprintf(" Size: 64MB (32Meg x 16bits)\n\n");
//
// The EPI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// For this example EPI0 is used with multiple pins on PortA, B, C, G, H,
// K, L, M and N. The actual port and pins used may be different on your
// part, consult the data sheet for more information.
// TODO: Update based upon the EPI pin assignment on your target part.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOK);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOL);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOM);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPION);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. Please refer to the datasheet for more information about pin
// muxing. Note that EPI0S27:20 are not used for the EPI SDRAM
// implementation.
// TODO: Update this section based upon the EPI pin assignment on your
// target part.
//
//
// EPI0S4 ~ EPI0S7: C4 ~ 7
//
ui32Val = HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL);
ui32Val &= 0x0000FFFF;
ui32Val |= 0xFFFF0000;
HWREG(GPIO_PORTC_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S8 ~ EPI0S9: A6 ~ 7
//
ui32Val = HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL);
ui32Val &= 0x00FFFFFF;
ui32Val |= 0xFF000000;
HWREG(GPIO_PORTA_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S10 ~ EPI0S11: G0 ~ 1
//
ui32Val = HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFFFF00;
ui32Val |= 0x000000FF;
HWREG(GPIO_PORTG_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S12 ~ EPI0S15: M0 ~ 3
//
ui32Val = HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTM_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S16 ~ EPI0S19: L0 ~ 3
//
ui32Val = HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0000;
ui32Val |= 0x0000FFFF;
HWREG(GPIO_PORTL_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S28 : B3
//
ui32Val = HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF0FFF;
ui32Val |= 0x0000F000;
HWREG(GPIO_PORTB_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S29 ~ EPI0S30: N2 ~ 3
//
ui32Val = HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL);
ui32Val &= 0xFFFF00FF;
ui32Val |= 0x0000FF00;
HWREG(GPIO_PORTN_BASE + GPIO_O_PCTL) = ui32Val;
//
// EPI0S00 ~ EPI0S03, EPI0S31 : K0 ~ 3, K5
//
ui32Val = HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL);
ui32Val &= 0xFF0F0000;
ui32Val |= 0x00F0FFFF;
HWREG(GPIO_PORTK_BASE + GPIO_O_PCTL) = ui32Val;
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
//
GPIOPinTypeEPI(GPIO_PORTA_BASE, EPI_PORTA_PINS);
GPIOPinTypeEPI(GPIO_PORTB_BASE, EPI_PORTB_PINS);
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTK_BASE, EPI_PORTK_PINS);
GPIOPinTypeEPI(GPIO_PORTL_BASE, EPI_PORTL_PINS);
GPIOPinTypeEPI(GPIO_PORTM_BASE, EPI_PORTM_PINS);
GPIOPinTypeEPI(GPIO_PORTN_BASE, EPI_PORTN_PINS);
//
// Is our current system clock faster than we can drive the SDRAM clock?
//
if(ui32SysClock > 60000000)
{
//
// Yes. Set the EPI clock to half the system clock.
//
EPIDividerSet(EPI0_BASE, 1);
}
else
{
//
// With a system clock of 60MHz or lower, we can drive the SDRAM at
// the same rate so set the divider to 0.
//
EPIDividerSet(EPI0_BASE, 0);
}
//
// Sets the usage mode of the EPI module. For this example we will use
// the SDRAM mode to talk to the external 64MB SDRAM daughter card.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Keep the compiler happy by setting a default value for the frequency
// flag.
//
ui32Freq = g_psSDRAMFreq[NUM_SDRAM_FREQ - 1].ui32FreqFlag;
//
// Examine the system clock frequency to determine how to set the SDRAM
// controller's frequency flag.
//
for(ui32Val = 0; ui32Val < NUM_SDRAM_FREQ; ui32Val++)
{
//
// Is the system clock frequency above the break point in the table?
//
if(ui32SysClock >= g_psSDRAMFreq[ui32Val].ui32SysClock)
{
//
// Yes - remember the frequency flag to use and exit the loop.
//
ui32Freq = g_psSDRAMFreq[ui32Val].ui32FreqFlag;
break;
}
}
//
// Configure the SDRAM mode. We configure the SDRAM according to our core
// clock frequency. We will use the normal (or full power) operating
// state which means we will not use the low power self-refresh state.
// Set the SDRAM size to 64MB with a refresh interval of 1024 clock ticks.
//
EPIConfigSDRAMSet(EPI0_BASE, (ui32Freq | EPI_SDRAM_FULL_POWER |
EPI_SDRAM_SIZE_512MBIT), 1024);
//
// Set the address map. The EPI0 is mapped from 0x60000000 to 0x01FFFFFF.
// For this example, we will start from a base address of 0x60000000 with
// a size of 256MB. Although our SDRAM is only 64MB, there is no 64MB
// aperture option so we pick the next larger size.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);
//
// Wait for the SDRAM wake-up to complete by polling the SDRAM
// initialization sequence bit. This bit is true when the SDRAM interface
// is going through the initialization and false when the SDRAM interface
// it is not in a wake-up period.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
}
//
// Set the EPI memory pointer to the base of EPI memory space. Note that
// g_pui16EPISdram is declared as volatile so the compiler should not
// optimize reads out of the memory. With this pointer, the memory space
// is accessed like a simple array.
//
g_pui16EPISdram = (uint16_t *)0x60000000;
//
// Read the initial data in SDRAM, and display it on the console.
//
UARTprintf(" SDRAM Initial Data:\n");
UARTprintf(" Mem[0x6000.0000] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS]);
UARTprintf(" Mem[0x6000.0001] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS + 1]);
UARTprintf(" Mem[0x603F.FFFE] = 0x%4x\n",
g_pui16EPISdram[SDRAM_END_ADDRESS - 1]);
UARTprintf(" Mem[0x603F.FFFF] = 0x%4x\n\n",
g_pui16EPISdram[SDRAM_END_ADDRESS]);
//
// Display what writes we are doing on the console.
//
UARTprintf(" SDRAM Write:\n");
UARTprintf(" Mem[0x6000.0000] <- 0xabcd\n");
UARTprintf(" Mem[0x6000.0001] <- 0x1234\n");
UARTprintf(" Mem[0x603F.FFFE] <- 0xdcba\n");
UARTprintf(" Mem[0x603F.FFFF] <- 0x4321\n\n");
//
// Write to the first 2 and last 2 address of the SDRAM card. Since the
// SDRAM card is word addressable, we will write words.
//
g_pui16EPISdram[SDRAM_START_ADDRESS] = 0xabcd;
g_pui16EPISdram[SDRAM_START_ADDRESS + 1] = 0x1234;
g_pui16EPISdram[SDRAM_END_ADDRESS - 1] = 0xdcba;
g_pui16EPISdram[SDRAM_END_ADDRESS] = 0x4321;
//
// Read back the data you wrote, and display it on the console.
//
UARTprintf(" SDRAM Read:\n");
UARTprintf(" Mem[0x6000.0000] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS]);
UARTprintf(" Mem[0x6000.0001] = 0x%4x\n",
g_pui16EPISdram[SDRAM_START_ADDRESS + 1]);
UARTprintf(" Mem[0x603F.FFFE] = 0x%4x\n",
g_pui16EPISdram[SDRAM_END_ADDRESS - 1]);
UARTprintf(" Mem[0x603F.FFFF] = 0x%4x\n\n",
g_pui16EPISdram[SDRAM_END_ADDRESS]);
//
// Check the validity of the data.
//
if((g_pui16EPISdram[SDRAM_START_ADDRESS] == 0xabcd) &&
(g_pui16EPISdram[SDRAM_START_ADDRESS + 1] == 0x1234) &&
(g_pui16EPISdram[SDRAM_END_ADDRESS - 1] == 0xdcba) &&
(g_pui16EPISdram[SDRAM_END_ADDRESS] == 0x4321))
{
//
// Read and write operations were successful. Return with no errors.
//
UARTprintf("Read and write to external SDRAM was successful!\n");
return(0);
}
//
// Display on the console that there was an error.
//
UARTprintf("Read and/or write failure!");
UARTprintf(" Check if your SDRAM card is plugged in.");
//
// Read and/or write operations were unsuccessful. Wait in while(1) loop
// for debugging.
//
while(1)
{
}
}
//*****************************************************************************
//
//! Initializes the SDRAM.
//!
//! \param ulEPIDivider is the EPI clock divider to use.
//! \param ulConfig is the SDRAM interface configuration.
//! \param ulRefresh is the refresh count in core clocks (0-2047).
//!
//! This function must be called prior to ExtRAMAlloc() or ExtRAMFree(). It
//! configures the Stellaris microcontroller EPI block for SDRAM access and
//! initializes the SDRAM heap (if SDRAM is found). The parameter \e ulConfig
//! is the logical OR of several sets of choices:
//!
//! The processor core frequency must be specified with one of the following:
//!
//! - \b EPI_SDRAM_CORE_FREQ_0_15 - core clock is 0 MHz < clk <= 15 MHz
//! - \b EPI_SDRAM_CORE_FREQ_15_30 - core clock is 15 MHz < clk <= 30 MHz
//! - \b EPI_SDRAM_CORE_FREQ_30_50 - core clock is 30 MHz < clk <= 50 MHz
//! - \b EPI_SDRAM_CORE_FREQ_50_100 - core clock is 50 MHz < clk <= 100 MHz
//!
//! The low power mode is specified with one of the following:
//!
//! - \b EPI_SDRAM_LOW_POWER - enter low power, self-refresh state
//! - \b EPI_SDRAM_FULL_POWER - normal operating state
//!
//! The SDRAM device size is specified with one of the following:
//!
//! - \b EPI_SDRAM_SIZE_64MBIT - 64 Mbit device (8 MB)
//! - \b EPI_SDRAM_SIZE_128MBIT - 128 Mbit device (16 MB)
//! - \b EPI_SDRAM_SIZE_256MBIT - 256 Mbit device (32 MB)
//! - \b EPI_SDRAM_SIZE_512MBIT - 512 Mbit device (64 MB)
//!
//! The parameter \e ulRefresh sets the refresh counter in units of core
//! clock ticks. It is an 11-bit value with a range of 0 - 2047 counts.
//!
//! \return Returns \b true on success of \b false if no SDRAM is found or
//! any other error occurs.
//
//*****************************************************************************
tBoolean
SDRAMInit(unsigned long ulEPIDivider, unsigned long ulConfig,
unsigned long ulRefresh)
{
//
// Enable the EPI peripheral
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// Configure the GPIO for communication with SDRAM.
//
#ifdef EPI_PORTA_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_GPIOPadConfigSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTA_BASE, EPI_PORTA_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_GPIOB_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_GPIOPadConfigSet(GPIO_PORTB_BASE, EPI_GPIOB_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTB_BASE, EPI_GPIOB_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTC_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_GPIOPadConfigSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTC_BASE, EPI_PORTC_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTD_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_GPIOPadConfigSet(GPIO_PORTD_BASE, EPI_PORTD_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTD_BASE, EPI_PORTD_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTE_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
ROM_GPIOPadConfigSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTE_BASE, EPI_PORTE_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTF_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
ROM_GPIOPadConfigSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTF_BASE, EPI_PORTF_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTG_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
ROM_GPIOPadConfigSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTG_BASE, EPI_PORTG_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTH_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
ROM_GPIOPadConfigSet(GPIO_PORTH_BASE, EPI_PORTH_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTH_BASE, EPI_PORTH_PINS, GPIO_DIR_MODE_HW);
#endif
#ifdef EPI_PORTJ_PINS
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
ROM_GPIOPadConfigSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_STRENGTH_2MA,
GPIO_PIN_TYPE_STD_WPU);
ROM_GPIODirModeSet(GPIO_PORTJ_BASE, EPI_PORTJ_PINS, GPIO_DIR_MODE_HW);
#endif
#if defined(EPI_CLK_PORT) && defined(EPI_CLK_PIN)
ROM_GPIOPadConfigSet(EPI_CLK_PORT, EPI_CLK_PIN, GPIO_STRENGTH_8MA,
GPIO_PIN_TYPE_STD_WPU);
#endif
//
// Set the EPI divider.
//
EPIDividerSet(EPI0_BASE, ulEPIDivider);
//
// Select SDRAM mode.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Configure SDRAM mode.
//
EPIConfigSDRAMSet(EPI0_BASE, ulConfig, ulRefresh);
//
// Set the address map.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_256MB | EPI_ADDR_RAM_BASE_6);
//
// Set the EPI mem pointer to the base of EPI mem
//
g_pusEPIMem = (unsigned short *)0x60000000;
//
// Wait for the EPI initialization to complete.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
//
// Wait for SDRAM initialization to complete.
//
}
//
// At this point, the SDRAM should be accessible. We attempt a couple
// of writes then read back the memory to see if it seems to be there.
//
g_pusEPIMem[0] = 0xABCD;
g_pusEPIMem[1] = 0x5AA5;
//
// Read back the patterns we just wrote to make sure they are valid. Note
// that we declared g_pusEPIMem as volatile so the compiler should not
// optimize these reads out of the image.
//
if((g_pusEPIMem[0] == 0xABCD) && (g_pusEPIMem[1] == 0x5AA5))
{
//
// The memory appears to be there so remember that we found it.
//
g_bSDRAMPresent = true;
//
// Now set up the heap that ExtRAMAlloc() and ExtRAMFree() will use.
//
bpool((void *)g_pusEPIMem, SDRAM_SIZE_BYTES);
}
//
// If we get this far, the SDRAM heap has been successfully initialized.
//
return(g_bSDRAMPresent);
}
//*****************************************************************************
//
// Configure EPI0 in SDRAM mode. The EPI memory space is setup using an a
// simple C array. This example shows how to read and write to an SDRAM card
// using the EPI bus in SDRAM mode.
//
//*****************************************************************************
void
sdram_init(void)
{
unsigned long ulClk, ulNsPerTick, ulConfig, ulRefresh;
//
// Display the setup on the console.
//
// UARTprintf("EPI SDRAM Mode ->\n");
// UARTprintf(" Type: SDRAM\n");
// UARTprintf(" Starting Address: 0x6000.0000\n");
// UARTprintf(" End Address: 0x603F.FFFF\n");
// UARTprintf(" Data: 16-bit\n");
// UARTprintf(" Size: 8MB (4Meg x 16bits)\n\n");
//
// The EPI0 peripheral must be enabled for use.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_EPI0);
//
// For this example EPI0 is used with multiple pins on PortC, E, F, G, H,
// and J. The actual port and pins used may be different on your part,
// consult the data sheet for more information.
// TODO: change this to whichever GPIO port you are using.
//
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
//
// This step configures the internal pin muxes to set the EPI pins for use
// with EPI. This step is only required because the default function of
// these pins may not be to function in EPI mode. Please reference the
// datasheet for more information about pin muxing. Note that EPI0S27:20
// are not used for the EPI SDRAM implementation.
// TODO: change this to select the port/pin you are using.
//
GPIOPinConfigure(GPIO_PH3_EPI0S0);
GPIOPinConfigure(GPIO_PH2_EPI0S1);
GPIOPinConfigure(GPIO_PC4_EPI0S2);
GPIOPinConfigure(GPIO_PC5_EPI0S3);
GPIOPinConfigure(GPIO_PC6_EPI0S4);
GPIOPinConfigure(GPIO_PC7_EPI0S5);
GPIOPinConfigure(GPIO_PH0_EPI0S6);
GPIOPinConfigure(GPIO_PH1_EPI0S7);
GPIOPinConfigure(GPIO_PE0_EPI0S8);
GPIOPinConfigure(GPIO_PE1_EPI0S9);
GPIOPinConfigure(GPIO_PH4_EPI0S10);
GPIOPinConfigure(GPIO_PH5_EPI0S11);
GPIOPinConfigure(GPIO_PF4_EPI0S12);
GPIOPinConfigure(GPIO_PG0_EPI0S13);
GPIOPinConfigure(GPIO_PG1_EPI0S14);
GPIOPinConfigure(GPIO_PF5_EPI0S15);
GPIOPinConfigure(GPIO_PJ0_EPI0S16);
GPIOPinConfigure(GPIO_PJ1_EPI0S17);
GPIOPinConfigure(GPIO_PJ2_EPI0S18);
GPIOPinConfigure(GPIO_PJ3_EPI0S19);
GPIOPinConfigure(GPIO_PJ4_EPI0S28);
GPIOPinConfigure(GPIO_PJ5_EPI0S29);
GPIOPinConfigure(GPIO_PJ6_EPI0S30);
GPIOPinConfigure(GPIO_PG7_EPI0S31);
//
// Configure the GPIO pins for EPI mode. All the EPI pins require 8mA
// drive strength in push-pull operation. This step also gives control of
// pins to the EPI module.
// TODO: change this to select the port/pin you are using.
//
GPIOPinTypeEPI(GPIO_PORTC_BASE, EPI_PORTC_PINS);
GPIOPinTypeEPI(GPIO_PORTE_BASE, EPI_PORTE_PINS);
GPIOPinTypeEPI(GPIO_PORTF_BASE, EPI_PORTF_PINS);
GPIOPinTypeEPI(GPIO_PORTG_BASE, EPI_PORTG_PINS);
GPIOPinTypeEPI(GPIO_PORTH_BASE, EPI_PORTH_PINS);
GPIOPinTypeEPI(GPIO_PORTJ_BASE, EPI_PORTJ_PINS);
//
// Now set the EPI operating mode for the daughter board detected. We need
// to determine some timing information based on the ID block we have and
// also the current system clock.
//
ulClk = ROM_SysCtlClockGet();
ulNsPerTick = 1000000000 / ulClk;
//
// Set the EPI clock divider to ensure a basic EPI clock rate no faster
// than defined via the ucRate0nS and ucRate1nS fields in the info
// structure.
//
EPIDividerSet(EPI0_BASE, CalcEPIDivider(ulNsPerTick));
// //
// // Sets the clock divider for the EPI module. In this case set the
// // divider to 0, making the EPIClock = SysClk.
// //
// EPIDividerSet(EPI0_BASE, 0);
//
// Sets the usage mode of the EPI module. For this example we will use
// the SDRAM mode to talk to the external 8MB SDRAM daughter card.
//
EPIModeSet(EPI0_BASE, EPI_MODE_SDRAM);
//
// Configure the SDRAM mode. We configure the SDRAM according to our core
// clock frequency, in this case we are in the 15 MHz < clk <= 30 MHz
// range (i.e 16Mhz crystal). We will use the normal (or full power)
// operating state which means we will not use the low power self-refresh
// state. Set the SDRAM size to 8MB (or 64Mb) with a refresh counter of
// 1024 clock ticks.
// TODO: change this to select the proper clock frequency and SDRAM
// refresh counter.
//
ulRefresh = 0;
ulConfig = SDRAMConfigGet(ulClk, &ulRefresh);
EPIConfigSDRAMSet(EPI0_BASE, ulConfig | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_64MBIT, 1024);
//
// Set the address map. The EPI0 is mapped from 0x60000000 to 0xCFFFFFFF.
// For this example, we will start from a base address of 0x60000000 with
// a size of 16MB. We use 16MB so we have the ability to access the
// entire 8MB SDRAM daughter card. Since there is no 8MB option, so we
// use the next closest one. If you attempt to access an address higher
// than 4Meg (since SDRAM mode uses 16-bit data, you have 4Meg of
// of addresses by 16-bits of data) a fault will not occur since we
// configured the EPI for 16MB addressability. In the case that you do
// access an address higher than 0x3FFFFF, the MSb of the address gets
// ignored.
//
EPIAddressMapSet(EPI0_BASE, EPI_ADDR_RAM_SIZE_16MB | EPI_ADDR_RAM_BASE_6);
//
// Wait for the SDRAM wake-up to complete by polling the SDRAM
// initialization sequence bit. This bit is true when the SDRAM interface
// is going through the initialization and false when the SDRAM interface
// it is not in a wake-up period.
//
while(HWREG(EPI0_BASE + EPI_O_STAT) & EPI_STAT_INITSEQ)
{
}
}