static bool enableIRQ(mrf::Object* obj, void*) { evgMrm *evg=dynamic_cast<evgMrm*>(obj); if(!evg) return true; /** * Enable PCIe interrputs (1<<30) * * Change by: tslejko * Reason: Support for cPCI EVG */ WRITE32(evg->getRegAddr(), IrqEnable, EVG_IRQ_PCIIE | //PCIe interrupt enable, EVG_IRQ_ENABLE | EVG_IRQ_EXT_INP | EVG_IRQ_STOP_RAM(0) | EVG_IRQ_STOP_RAM(1) | EVG_IRQ_START_RAM(0) | EVG_IRQ_START_RAM(1) ); // WRITE32(pReg, IrqEnable, // EVG_IRQ_ENABLE | // EVG_IRQ_STOP_RAM1 | // EVG_IRQ_STOP_RAM0 | // EVG_IRQ_START_RAM1 | // EVG_IRQ_START_RAM0 | // EVG_IRQ_EXT_INP | // EVG_IRQ_DBUFF | // EVG_IRQ_FIFO | // EVG_IRQ_RXVIO // ); return true; }
void evgSeqRam::dealloc() { m_softSeq = 0; //clear interrupt flags BITSET32(m_pReg, IrqFlag, EVG_IRQ_STOP_RAM(m_id)); BITSET32(m_pReg, IrqFlag, EVG_IRQ_START_RAM(m_id)); }