void WDOG_Init(WDOG_Type *base, const wdog_config_t *config)
{
assert(config);
uint32_t value = 0U;
uint32_t primaskValue = 0U;
value = WDOG_STCTRLH_WDOGEN(config->enableWdog) | WDOG_STCTRLH_CLKSRC(config->clockSource) |
WDOG_STCTRLH_IRQRSTEN(config->enableInterrupt) | WDOG_STCTRLH_WINEN(config->enableWindowMode) |
WDOG_STCTRLH_ALLOWUPDATE(config->enableUpdate) | WDOG_STCTRLH_DBGEN(config->workMode.enableDebug) |
WDOG_STCTRLH_STOPEN(config->workMode.enableStop) |
#if defined(FSL_FEATURE_WDOG_HAS_WAITEN) && FSL_FEATURE_WDOG_HAS_WAITEN
WDOG_STCTRLH_WAITEN(config->workMode.enableWait) |
#endif /* FSL_FEATURE_WDOG_HAS_WAITEN */
WDOG_STCTRLH_DISTESTWDOG(1U);
/* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
* and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
primaskValue = DisableGlobalIRQ();
WDOG_Unlock(base);
/* Wait one bus clock cycle */
base->RSTCNT = 0U;
/* Set configruation */
base->PRESC = WDOG_PRESC_PRESCVAL(config->prescaler);
base->WINH = (uint16_t)((config->windowValue >> 16U) & 0xFFFFU);
base->WINL = (uint16_t)((config->windowValue) & 0xFFFFU);
base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU);
base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU);
base->STCTRLH = value;
EnableGlobalIRQ(primaskValue);
}
/*!
* brief Initializes the RTWDOG module.
*
* This function initializes the RTWDOG.
* To reconfigure the RTWDOG without forcing a reset first, enableUpdate must be set to true
* in the configuration.
*
* Example:
* code
* rtwdog_config_t config;
* RTWDOG_GetDefaultConfig(&config);
* config.timeoutValue = 0x7ffU;
* config.enableUpdate = true;
* RTWDOG_Init(wdog_base,&config);
* endcode
*
* param base RTWDOG peripheral base address.
* param config The configuration of the RTWDOG.
*/
void RTWDOG_Init(RTWDOG_Type *base, const rtwdog_config_t *config)
{
assert(config);
uint32_t value = 0U;
uint32_t primaskValue = 0U;
value = RTWDOG_CS_EN(config->enableRtwdog) | RTWDOG_CS_CLK(config->clockSource) |
RTWDOG_CS_INT(config->enableInterrupt) | RTWDOG_CS_WIN(config->enableWindowMode) |
RTWDOG_CS_UPDATE(config->enableUpdate) | RTWDOG_CS_DBG(config->workMode.enableDebug) |
RTWDOG_CS_STOP(config->workMode.enableStop) | RTWDOG_CS_WAIT(config->workMode.enableWait) |
RTWDOG_CS_PRES(config->prescaler) | RTWDOG_CS_CMD32EN(true) | RTWDOG_CS_TST(config->testMode);
/* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
* and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
primaskValue = DisableGlobalIRQ();
RTWDOG_Unlock(base);
base->WIN = config->windowValue;
base->TOVAL = config->timeoutValue;
base->CS = value;
while ((base->CS & RTWDOG_CS_RCS_MASK) == 0)
{
}
EnableGlobalIRQ(primaskValue);
}
/*! *********************************************************************************
* \brief Read command for reading from IFR using RDINDEX command
*
* \param read_addr flash address
*
* \return 8 bytes of packed data containing radio trims only
*
***********************************************************************************/
uint64_t read_index_ifr(uint32_t read_addr)
{
uint8_t rdindex = read_addr;
uint64_t read_data;
uint8_t i;
uint32_t primask;
while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */
if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
{
FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFE->FCCOB[0] = RDINDX;
FTFE->FCCOB[1] = rdindex;
primask = DisableGlobalIRQ();
FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
EnableGlobalIRQ(primask);
/* Pack read data back into 64 bit type */
read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */
for (i = 10; i > 3; i--)
{
read_data = read_data << 8;
read_data |= FTFE->FCCOB[i];
}
return read_data;
}
void EWM_Refresh(EWM_Type *base)
{
uint32_t primaskValue = 0U;
/* Disable the global interrupt to protect refresh sequence */
primaskValue = DisableGlobalIRQ();
base->SERV = (uint8_t)0xB4U;
base->SERV = (uint8_t)0x2CU;
EnableGlobalIRQ(primaskValue);
}
void WDOG_Refresh(WDOG_Type *base)
{
uint32_t primaskValue = 0U;
/* Disable the global interrupt to protect refresh sequence */
primaskValue = DisableGlobalIRQ();
base->REFRESH = WDOG_FIRST_WORD_OF_REFRESH;
base->REFRESH = WDOG_SECOND_WORD_OF_REFRESH;
EnableGlobalIRQ(primaskValue);
}
/*!
* brief De-initializes the RTWDOG module.
*
* This function shuts down the RTWDOG.
* Ensure that the WDOG_CS.UPDATE is 1, which means that the register update is enabled.
*
* param base RTWDOG peripheral base address.
*/
void RTWDOG_Deinit(RTWDOG_Type *base)
{
uint32_t primaskValue = 0U;
/* Disable the global interrupts */
primaskValue = DisableGlobalIRQ();
RTWDOG_Unlock(base);
RTWDOG_Disable(base);
EnableGlobalIRQ(primaskValue);
}
void WDOG_Deinit(WDOG_Type *base)
{
uint32_t primaskValue = 0U;
/* Disable the global interrupts */
primaskValue = DisableGlobalIRQ();
WDOG_Unlock(base);
/* Wait one bus clock cycle */
base->RSTCNT = 0U;
WDOG_Disable(base);
EnableGlobalIRQ(primaskValue);
WDOG_ClearResetCount(base);
}
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
return ret;
}
uint64_t read_resource_ifr(uint32_t read_addr)
{
uint32_t primask;
uint64_t packed_data;
uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
uint8_t read_data[8];
uint64_t temp_64;
uint8_t i;
flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK )
{
FTFE->FSTAT = (1<<FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFE->FCCOB0 = RDRSRC;
FTFE->FCCOB1 = flash_addr23_16;
FTFE->FCCOB2 = flash_addr15_8;
FTFE->FCCOB3 = flash_addr7_0;
FTFE->FCCOB4 = 0x00;
primask = DisableGlobalIRQ();
FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK;
while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */
EnableGlobalIRQ(primask);
/* Start reading */
read_data[7] = FTFE->FCCOB4;
read_data[6] = FTFE->FCCOB5;
read_data[5] = FTFE->FCCOB6;
read_data[4] = FTFE->FCCOB7;
read_data[3] = FTFE->FCCOB8;
read_data[2] = FTFE->FCCOB9;
read_data[1] = FTFE->FCCOBA;
read_data[0] = FTFE->FCCOBB;
packed_data = 0;
for (i = 0; i < 8; i++)
{
temp_64 = read_data[i];
packed_data |= temp_64 << (i * 8);
}
return packed_data;
}
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
#elif defined(__ICCARM__)
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
#elif defined(__GNUC__)
extern uint32_t __VECTOR_TABLE[];
extern uint32_t __VECTOR_RAM[];
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
#endif /* defined(__CC_ARM) */
uint32_t n;
uint32_t ret;
uint32_t irqMaskValue;
irqMaskValue = DisableGlobalIRQ();
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
{
/* Copy the vector table from ROM to RAM */
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
{
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
}
/* Point the VTOR to the position of vector table */
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
ret = __VECTOR_RAM[irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
__VECTOR_RAM[irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
return ret;
}
uint32_t read_resource_ifr(uint32_t read_addr)
{
uint32_t primask;
uint32_t packed_data;
uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0;
uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0;
flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16);
flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8);
flash_addr7_0 = (uint8_t)(read_addr & 0xFF);
while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK )
{
FTFA->FSTAT = (1<<FTFA_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */
}
FTFA->FCCOB0 = RDRSRC;
FTFA->FCCOB1 = flash_addr23_16;
FTFA->FCCOB2 = flash_addr15_8;
FTFA->FCCOB3 = flash_addr7_0;
FTFA->FCCOB8 = 0x00;
primask = DisableGlobalIRQ();
FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK;
while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */
EnableGlobalIRQ(primask);
/* Start reading */
read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */
read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */
read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */
read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */
packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0);
return packed_data;
}
void WDOG_SetTestModeConfig(WDOG_Type *base, wdog_test_config_t *config)
{
assert(config);
uint32_t value = 0U;
uint32_t primaskValue = 0U;
value = WDOG_STCTRLH_DISTESTWDOG(0U) | WDOG_STCTRLH_TESTWDOG(1U) | WDOG_STCTRLH_TESTSEL(config->testMode) |
WDOG_STCTRLH_BYTESEL(config->testedByte) | WDOG_STCTRLH_IRQRSTEN(0U) | WDOG_STCTRLH_WDOGEN(1U) |
WDOG_STCTRLH_ALLOWUPDATE(1U);
/* Disable the global interrupts. Otherwise, an interrupt could effectively invalidate the unlock sequence
* and the WCT may expire. After the configuration finishes, re-enable the global interrupts. */
primaskValue = DisableGlobalIRQ();
WDOG_Unlock(base);
/* Wait one bus clock cycle */
base->RSTCNT = 0U;
/* Set configruation */
base->TOVALH = (uint16_t)((config->timeoutValue >> 16U) & 0xFFFFU);
base->TOVALL = (uint16_t)((config->timeoutValue) & 0xFFFFU);
base->STCTRLH = value;
EnableGlobalIRQ(primaskValue);
}
static status_t SPDIF_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config, uint32_t rightChannel)
{
edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
uint32_t primask;
uint32_t csr;
int8_t currentTcd;
int8_t previousTcd;
int8_t nextTcd;
/* Check if tcd pool is full. */
primask = DisableGlobalIRQ();
if (handle->tcdUsed >= handle->tcdSize)
{
EnableGlobalIRQ(primask);
return kStatus_EDMA_QueueFull;
}
currentTcd = handle->tail;
handle->tcdUsed++;
/* Calculate index of next TCD */
nextTcd = currentTcd + 1U;
if (nextTcd == handle->tcdSize)
{
nextTcd = 0U;
}
/* Advance queue tail index */
handle->tail = nextTcd;
EnableGlobalIRQ(primask);
/* Calculate index of previous TCD */
previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
/* Configure current TCD block. */
EDMA_TcdReset(&handle->tcdPool[currentTcd]);
EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
/* Set channel link */
EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MinorLink, rightChannel);
EDMA_TcdSetChannelLink(&handle->tcdPool[currentTcd], kEDMA_MajorLink, rightChannel);
/* Enable major interrupt */
handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
/* Link current TCD with next TCD for identification of current TCD */
handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
/* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
if (currentTcd != previousTcd)
{
/* Enable scatter/gather feature in the previous TCD block. */
csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
handle->tcdPool[previousTcd].CSR = csr;
/*
Check if the TCD blcok in the registers is the previous one (points to current TCD block). It
is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
before link the previous TCD block.
*/
if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
{
/* Enable scatter/gather also in the TCD registers. */
csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
/* Must write the CSR register one-time, because the transfer maybe finished anytime. */
tcdRegs->CSR = csr;
/*
It is very important to check the ESG bit!
Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
the current TCD block has been loaded into TCD registers), it means transfer finished
and TCD link operation fail, so must install TCD content into TCD registers and enable
transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic
link succeed.
*/
if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
{
return kStatus_Success;
}
/*
Check whether the current TCD block is already loaded in the TCD registers. It is another
condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
TCD block has been loaded into TCD registers.
*/
if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
{
return kStatus_Success;
}
/*
If go to this, means the previous transfer finished, and the DONE bit is set.
So shall configure TCD registers.
*/
}
else if (tcdRegs->DLAST_SGA != 0)
{
/* The current TCD block has been linked successfully. */
return kStatus_Success;
}
else
{
/*
DLAST_SGA is 0 and it means the first submit transfer, so shall configure
TCD registers.
*/
}
}
/* There is no live chain, TCD block need to be installed in TCD registers. */
EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
/* Enable channel request again. */
if (handle->flags & 0x80)
{
handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
}
return kStatus_Success;
}
