//************************************************************************** // FREQVOLTSVC::runP8BuildPstateDataBlock //************************************************************************** errlHndl_t runP8BuildPstateDataBlock( const TARGETING::Target * i_procChip, PstateSuperStructure * o_data) { errlHndl_t l_err = NULL; // Assert on NULL input target assert(i_procChip != NULL); // convert to fapi target fapi::Target l_fapiProcChip(fapi::TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> (const_cast<TARGETING::Target*>(i_procChip)) ); FAPI_INVOKE_HWP(l_err, p8_build_pstate_datablock,l_fapiProcChip,o_data); if( l_err != NULL) { TRACFCOMP( g_fapiTd,ERR_MRK"Error from HWP: " "p8_build_pstate_datablock for target HUID: 0x%08X", i_procChip->getAttr<TARGETING::ATTR_HUID>()); } return l_err; }
// // Wrapper function to call proc_fbc_eff_config_aggregate // void* call_host_fbc_eff_config_aggregate( void *io_pArgs ) { errlHndl_t l_errl = NULL; ISTEP_ERROR::IStepError l_stepError; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_fbc_eff_config_aggregate entry" ); TARGETING::TargetHandleList l_procChips; getAllChips( l_procChips, TARGETING::TYPE_PROC); for (const auto & l_procChip: l_procChips) { fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2CpuTarget(l_procChip); FAPI_INVOKE_HWP(l_errl,p9_fbc_eff_config_aggregate,l_fapi2CpuTarget); if(l_errl) { l_stepError.addErrorDetails(l_errl); TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR : call_proc_fbc_eff_config_aggregate, PLID=0x%x", l_errl->plid() ); errlCommit(l_errl, HWPF_COMP_ID); } } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_fbc_eff_config_aggregate exit" ); return l_stepError.getErrorHandle(); }
void* call_cen_arrayinit (void *io_pArgs) { IStepError l_StepError; errlHndl_t l_err = NULL; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_arrayinit entry" ); TARGETING::TargetHandleList l_membufTargetList; getAllChips(l_membufTargetList, TYPE_MEMBUF); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_arrayinit: %d membufs found", l_membufTargetList.size()); for (const auto & l_membuf_target : l_membufTargetList) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "cen_arrayinit HWP target HUID %.8x", TARGETING::get_huid(l_membuf_target)); // call the HWP with each target fapi2::Target <fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_membuf_target (l_membuf_target); FAPI_INVOKE_HWP(l_err, cen_arrayinit, l_fapi_membuf_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: cen_arrayinit HWP on target HUID %.8x", l_err->reasonCode(), TARGETING::get_huid(l_membuf_target) ); // capture the target data in the elog ErrlUserDetailsTarget(l_membuf_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred l_StepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : cen_arrayinit HWP"); } } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_arrayinit exit" ); return l_StepError.getErrorHandle(); }
//************************************************************************** // FREQVOLTSVC::runProcGetVoltage //************************************************************************** errlHndl_t runProcGetVoltage( TARGETING::Target * io_procChip, const uint32_t i_bootFreqMhz) { TRACDCOMP(g_fapiTd,INFO_MRK"Enter runProcGetVoltage"); uint8_t l_vdd_vid = 0; uint8_t l_vcs_vid = 0; errlHndl_t l_err = NULL; TARGETING::ATTR_BOOT_VOLTAGE_type l_boot_voltage_info = PROC_BOOT_VOLT_PORT0_ENABLE; TRACDCOMP(g_fapiTd,INFO_MRK"i_bootFreqMhz: 0x%08X",i_bootFreqMhz); // Assert on NULL input target // If the target is NULL, we have NO functional PROCS. // Terminate IPL assert(io_procChip != NULL); // convert to fapi target fapi::Target l_fapiProcChip(fapi::TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> (const_cast<TARGETING::Target*>(io_procChip))); // Invoke HW procedure FAPI_INVOKE_HWP(l_err, proc_get_voltage,l_fapiProcChip,i_bootFreqMhz, l_vdd_vid,l_vcs_vid); if( l_err != NULL) { TRACFCOMP( g_fapiTd,ERR_MRK"Error from HWP: proc_get_voltage: " "i_bootFreq: 0x%08X, " "HUID: 0x%08X", i_bootFreqMhz, io_procChip->getAttr<TARGETING::ATTR_HUID>()); } TRACDCOMP(g_fapiTd,INFO_MRK"Vdd: 0x%02x, vcs: 0x%02x", l_vdd_vid, l_vcs_vid); // create boot voltage value l_boot_voltage_info |= ( ( static_cast<uint32_t>(l_vdd_vid) << PROC_BOOT_VOLT_VDD_SHIFT) & ( PROC_BOOT_VOLT_VDD_MASK ) ); l_boot_voltage_info |= ( ( static_cast<uint32_t>(l_vcs_vid) << PROC_BOOT_VOLT_VCS_SHIFT) & ( PROC_BOOT_VOLT_VDD_MASK ) ); // set ATTR_PROC_BOOT_VOLTAGE_VID io_procChip->setAttr< TARGETING::ATTR_PROC_BOOT_VOLTAGE_VID>( l_boot_voltage_info ); return l_err; }
/** * @brief Stop OCC for specified DCM pair of processors. * If 2nd input is NULL, OCC will be setup on just * one target. * * @param[in] i_target0: target of first processor in DCM pair * @param[in] i_target1: target of second processor in DCM pair * * @return errlHndl_t Error log of stopOCC failed */ errlHndl_t stopOCC(TARGETING::Target * i_target0, TARGETING::Target * i_target1) { TRACFCOMP( g_fapiTd, ENTER_MRK"stopOCC"); errlHndl_t err = NULL; do { const fapi::Target l_fapiTarg0(fapi::TARGET_TYPE_PROC_CHIP, (const_cast<TARGETING::Target*>(i_target0))); fapi::Target l_fapiTarg1; if(i_target1) { l_fapiTarg1.setType(fapi::TARGET_TYPE_PROC_CHIP); l_fapiTarg1.set(const_cast<TARGETING::Target*>(i_target1)); } else { l_fapiTarg1.setType(fapi::TARGET_TYPE_NONE); } FAPI_INVOKE_HWP( err, p8_pm_prep_for_reset, l_fapiTarg0, l_fapiTarg1, PM_RESET ); if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"stopOCC:p8_pm_prep_for_reset failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } } while(0); TRACFCOMP( g_fapiTd, EXIT_MRK"stopOCC"); return err; }
void* call_host_revert_sbe_mcs_setup( void *io_pArgs ) { errlHndl_t l_err = NULL; ISTEP_ERROR::IStepError l_stepError; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_revert_sbe_mcs_setup entry" ); TARGETING::Target * l_masterProc; TARGETING::targetService().masterProcChipTargetHandle( l_masterProc ); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running p9_revert_sbe_mcs_setup on " "target HUID %.8X", TARGETING::get_huid(l_masterProc)); // cast the target to a fapi2 target fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_master_proc( l_masterProc ); //Invode p9_revert_sbe_mcs_setup FAPI_INVOKE_HWP( l_err, p9_revert_sbe_mcs_setup, l_fapi_master_proc ); if (l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9_revert_sbe_mcs_setup", l_err->reasonCode()); // Create IStep error log and cross reference error l_stepError.addErrorDetails(l_err); // Commit error errlCommit(l_err,SBE_COMP_ID); } TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_revert_sbe_mcs_setup exit" ); return l_stepError.getErrorHandle(); }
/** * @brief Retrieve the SHA512 hash for the currently flashed explorer * firmware image. * * @param[in] i_target Target of the OCMB chip to retrieve the SHA512 hash * @param[out] o_regs Structure for storing the retrieved SHA512 hash * * @return NULL on success. Non-null on failure. */ errlHndl_t getFlashedHash(TargetHandle_t i_target, sha512regs_t& o_regs) { fapi2::buffer<uint64_t> l_scomBuffer; uint8_t* l_scomPtr = reinterpret_cast<uint8_t*>(l_scomBuffer.pointer()); fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2Target(i_target); errlHndl_t l_err = nullptr; //Start addres of hash register (a.k.a. RAM1 register) const uint32_t HASH_REG_ADDR = 0x00002200; // loop until we've filled the sha512regs_t struct for(uint32_t l_bytesCopied = 0; l_bytesCopied < sizeof(sha512regs_t); l_bytesCopied += sizeof(uint32_t)) { // Use getScom, this knows internally whether to use i2c or inband FAPI_INVOKE_HWP(l_err, getScom, l_fapi2Target, HASH_REG_ADDR + l_bytesCopied, l_scomBuffer); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "getFlashedHash: Failed reading SHA512 hash from" " ocmb[0x%08x]. bytesCopied[%u]", TARGETING::get_huid(i_target), l_bytesCopied); break; } // copy scom buffer into the unformatted uint8_t array. // Even though the scom buffer is 8 bytes, only 4 bytes are read and // copied into the least significant 4 bytes. memcpy(&o_regs.unformatted[l_bytesCopied], l_scomPtr + sizeof(uint32_t), sizeof(uint32_t)); } return l_err; }
void* call_dmi_pre_trainadv (void *io_pArgs) { IStepError l_StepError; errlHndl_t l_err = NULL; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv entry" ); TARGETING::TargetHandleList l_dmiTargetList; getAllChiplets(l_dmiTargetList, TYPE_DMI); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv: %d DMIs found", l_dmiTargetList.size()); for (const auto & l_dmi_target : l_dmiTargetList) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "p9_io_dmi_pre_trainadv HWP target HUID %.8x", TARGETING::get_huid(l_dmi_target)); //get the membuf associated with this DMI. TARGETING::TargetHandleList l_pChildMembufList; getChildAffinityTargetsByState(l_pChildMembufList, l_dmi_target, CLASS_CHIP, TYPE_MEMBUF, UTIL_FILTER_PRESENT); // call the HWP p9_io_dmi_pre_trainadv only if membuf connected. //we can't expect more than one membufs connected to a DMI if (l_pChildMembufList.size() == 1) { // call the HWP with each DMI target fapi2::Target<fapi2::TARGET_TYPE_DMI> l_fapi_dmi_target (l_dmi_target); fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapi_membuf_target (l_pChildMembufList[0]); FAPI_INVOKE_HWP(l_err, p9_io_dmi_pre_trainadv, l_fapi_dmi_target, l_fapi_membuf_target ); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9_io_dmi_pre_trainadv HWP on target HUID %.8x", l_err->reasonCode(), TARGETING::get_huid(l_dmi_target) ); // capture the target data in the elog ErrlUserDetailsTarget(l_dmi_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred l_StepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : p9_io_dmi_pre_trainadv HWP"); } } else //No associated membuf { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "p9_io_dmi_pre_trainadv HWP skipped, no associated membufs %d" ,l_pChildMembufList.size()); } } TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv exit" ); // end task, returning any errorlogs to IStepDisp return l_StepError.getErrorHandle(); }
uint32_t rcTestCalloutNoneDeconfig() { uint32_t l_result = 0; errlHndl_t l_errl = NULL; bool l_hw_callout_found = false; FAPI_INF("rcTestCalloutNoneDeconfig running"); TARGETING::TargetHandleList l_dimmList; TARGETING::getAllLogicalCards(l_dimmList, TARGETING::TYPE_DIMM, false); TARGETING::Target * l_Dimm = NULL; //Take the first dimm if (l_dimmList.size() > 0) { l_Dimm = l_dimmList[0]; } else { TS_FAIL("No dimms found"); } //Convert to fapi2 target for the HWP below fapi2::Target<fapi2::TARGET_TYPE_DIMM> fapi2_dimmTarget(l_Dimm); FAPI_INVOKE_HWP(l_errl, p9_deconfigCalloutNone, fapi2_dimmTarget); if(l_errl != NULL) { FAPI_INF("rcTestCalloutNoneDeconfig: p9_deconfigCalloutNone " "returned errl (expected)"); //Get the User Data fields of the errl. They are returned as //vector<void*>, so iterate over them. for( auto l_callout_raw : l_errl-> getUDSections( ERRL_COMP_ID, ERRORLOG::ERRL_UDT_CALLOUT ) ) { HWAS::callout_ud_t* l_callout_entry = reinterpret_cast<HWAS::callout_ud_t*>(l_callout_raw); if(l_callout_entry->type == HWAS::HW_CALLOUT) { l_hw_callout_found = true; FAPI_INF("rcTestCalloutNoneDeconfig: hw callout found"); if(l_callout_entry->deconfigState == HWAS::DELAYED_DECONFIG) { FAPI_INF("rcTestCalloutNoneDeconfig: Target is deconfigured"); } else { TS_FAIL("rcTestCalloutNoneDeconfig: Target is NOT deconfigured"); l_result = 1; break; } } } if(!l_hw_callout_found) { TS_FAIL("rcTestCalloutNoneDeconfig: hw callout NOT found"); l_result = 2; } } else { TS_FAIL("rcTestCalloutNoneDeconfig: No error was returned from" " p9_deconfigCalloutNone !!"); l_result = 3; } //l_errl->setSev(ERRORLOG::ERRL_SEV_RECOVERED); //errlCommit(l_errl,CXXTEST_COMP_ID); delete l_errl; l_errl = NULL; // Now try it the way HWP people do it ReturnCode l_rc; FAPI_EXEC_HWP(l_rc, p9_deconfigCalloutNone, fapi2_dimmTarget); if (l_rc != fapi2::FAPI2_RC_SUCCESS) { // log the error but don't fail the unit test FAPI_INF("rcTestCalloutNoneDeconfig: logError called"); fapi2::logError(l_rc, fapi2::FAPI2_ERRL_SEV_RECOVERED, true); } else { TS_FAIL("rcTestCalloutNoneDeconfig: No error was returned from " "FAPI_EXEC_HWP p9_deconfigCalloutNone !!"); l_result = 4; } FAPI_INF("rcTestCalloutNoneDeconfig finished"); return l_result; }
uint32_t rcTestCalloutDeconfigGard() { uint32_t l_result = 0; errlHndl_t l_errl = NULL; bool l_hw_callout_found = false; FAPI_INF("rcTestCalloutDeconfigGard running"); TARGETING::TargetHandleList l_chipList; TARGETING::getAllChips(l_chipList, TARGETING::TYPE_PROC, false); TARGETING::Target * l_Proc = NULL; //Grab the first chip if there are multiple if (l_chipList.size() > 0) { l_Proc = l_chipList[0]; } else { TS_FAIL("No proc chips found"); } //Convert to fapi2 target for the HWP below fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> fapi2_procTarget(l_Proc); FAPI_INVOKE_HWP(l_errl, p9_gardAndDeconfig, fapi2_procTarget); if(l_errl != NULL) { FAPI_INF("rcTestCalloutDeconfigGard: p9_gardAndDeconfig " "returned errl (expected)"); //Get the User Data fields of the errl. They are returned as //vector<void*>, so iterate over them. for( auto l_callout_raw : l_errl-> getUDSections( ERRL_COMP_ID, ERRORLOG::ERRL_UDT_CALLOUT ) ) { HWAS::callout_ud_t* l_callout_entry = reinterpret_cast<HWAS::callout_ud_t*>(l_callout_raw); if(l_callout_entry->type == HWAS::HW_CALLOUT) { l_hw_callout_found = true; FAPI_INF("rcTestCalloutDeconfigGard: found hw callout"); if(l_callout_entry->gardErrorType == HWAS::GARD_Unrecoverable) { FAPI_INF("rcTestCalloutDeconfigGard: " "Gard Error Type matches"); } else { TS_FAIL("rcTestCalloutDeconfigGard: " "Gard Error Type does NOT match. Expected: %x Actual: %x", HWAS::GARD_Unrecoverable, l_callout_entry->gardErrorType); l_result = 1; break; } if(l_callout_entry->deconfigState == HWAS::DELAYED_DECONFIG) { FAPI_INF("rcTestCalloutDeconfigGard: Target deconfigured"); } else { TS_FAIL("rcTestCalloutDeconfigGard: " "Target is NOT deconfigured"); l_result = 2; break; } } } if(!l_hw_callout_found) { TS_FAIL("rcTestCalloutDeconfigGard: hw callout not found"); l_result = 3; } } else { TS_FAIL("rcTestCalloutDeconfigGard: No error was returned " "from p9_gardAndDeconfig !!"); l_result = 4; } delete l_errl; l_errl = NULL; FAPI_INF("rcTestCalloutDeconfigGard finished"); return l_result; }
uint32_t rcTestCalloutDeconfig() { uint32_t l_result = 0; errlHndl_t l_errl = NULL; bool l_hw_callout_found = false; FAPI_INF("rcTestCalloutDeconfig running"); TARGETING::TargetHandleList l_dimmList; TARGETING::getAllLogicalCards(l_dimmList, TARGETING::TYPE_DIMM, false); TARGETING::Target * l_Dimm = NULL; //Take the first dimm if (l_dimmList.size() > 0) { l_Dimm = l_dimmList[0]; } else { TS_FAIL("No dimms found"); } //Convert to fapi2 target for the HWP below fapi2::Target<fapi2::TARGET_TYPE_DIMM> fapi2_dimmTarget(l_Dimm); FAPI_INVOKE_HWP(l_errl, p9_deconfigCallout, fapi2_dimmTarget); if(l_errl != NULL) { FAPI_INF("rcTestCalloutDeconfig: p9_deconfigCallout returned errl " "(expected)"); //Get the User Data fields of the errl. They are returned as //vector<void*>, so iterate over them. for( auto l_callout_raw : l_errl-> getUDSections( ERRL_COMP_ID, ERRORLOG::ERRL_UDT_CALLOUT ) ) { HWAS::callout_ud_t* l_callout_entry = reinterpret_cast<HWAS::callout_ud_t*>(l_callout_raw); if(l_callout_entry->type == HWAS::HW_CALLOUT) { l_hw_callout_found = true; FAPI_INF("rcTestCalloutDeconfig: hw callout found"); if(l_callout_entry->deconfigState == HWAS::DELAYED_DECONFIG) { FAPI_INF("rcTestCalloutDeconfig: Target is deconfigured"); } else { TS_FAIL("rcTestCalloutDeconfig: Target is NOT deconfigured"); l_result = 1; break; } } } if(!l_hw_callout_found) { TS_FAIL("rcTestCalloutDeconfig: hw callout NOT found"); l_result = 2; } } else { TS_FAIL("rcTestCalloutDeconfig: No error was returned from" " p9_deconfigCallout !!"); l_result = 3; } delete l_errl; l_errl = NULL; FAPI_INF("rcTestCalloutDeconfig finished"); return l_result; }
uint32_t rcTestCalloutHw() { uint32_t l_result = 0; errlHndl_t l_errl = NULL; bool l_hw_callout_found = false; FAPI_INF("rcTestCalloutHw running"); TARGETING::TargetHandleList l_coreList; TARGETING::getAllChiplets(l_coreList, TARGETING::TYPE_CORE, false); TARGETING::Target * l_Core = NULL; //Get the first core if(l_coreList.size() > 0) { l_Core = l_coreList[0]; } else { TS_FAIL("No cores found"); } //Convert to fapi2 target for HWP fapi2::Target<fapi2::TARGET_TYPE_CORE> fapi2_coreTarget(l_Core); FAPI_INVOKE_HWP(l_errl, p9_hwCallout, fapi2_coreTarget); if(l_errl != NULL) { FAPI_INF("rcTestCalloutHw: p9_hwCallout returned errl (expected)"); //Get the User Data fields of the errl. They are returned as //vector<void*>, so iterate over them. for( auto l_callout_raw : l_errl-> getUDSections( ERRL_COMP_ID, ERRORLOG::ERRL_UDT_CALLOUT ) ) { HWAS::callout_ud_t* l_callout_entry = reinterpret_cast<HWAS::callout_ud_t*>(l_callout_raw); if(l_callout_entry->type == HWAS::HW_CALLOUT) { l_hw_callout_found = true; FAPI_INF("rcTestCalloutHw: hw callout found"); if(l_callout_entry->priority == HWAS::SRCI_PRIORITY_LOW) { FAPI_INF("rcTestCalloutHw: low priority hw callout found"); } else { TS_FAIL("rcTestCalloutHw: incorrect hw callout priority." " Expected: %x Actual: %x", HWAS::SRCI_PRIORITY_LOW, l_callout_entry->priority); l_result = 1; break; } } } if(!l_hw_callout_found) { TS_FAIL("rcTestCalloutHw: hw callout NOT found"); l_result = 2; } } else { TS_FAIL("rcTestCalloutHw: No error was returned from p9_hwCallout !!"); l_result = 3; } delete l_errl; l_errl = NULL; FAPI_INF("rcTestCalloutHw finished"); return l_result; }
uint32_t rcTestCalloutProcedure() { uint32_t l_result = 0; errlHndl_t l_errl = NULL; bool l_procedure_found = false; FAPI_INF("rcTestCalloutProcedure running"); FAPI_INVOKE_HWP(l_errl, p9_procedureCallout); if(l_errl != NULL) { FAPI_INF("rcTestCalloutProcedure: " "p9_procedureCallout returned errl (expected)"); //Get the User Data fields of the errl. They are returned as //vector<void*>, so iterate over them. for( auto l_callout_raw : l_errl-> getUDSections( ERRL_COMP_ID, ERRORLOG::ERRL_UDT_CALLOUT ) ) { HWAS::callout_ud_t* l_callout_entry = reinterpret_cast<HWAS::callout_ud_t*>(l_callout_raw); if(l_callout_entry->type == HWAS::PROCEDURE_CALLOUT) { l_procedure_found = true; FAPI_INF("rcTestCalloutProcedure: procedure callout found"); if(l_callout_entry->priority == HWAS::SRCI_PRIORITY_HIGH) { FAPI_INF("rcTestCalloutProcedure: " "high priority procedure callout found"); } else { TS_FAIL("rcTestCalloutProcedure: " "incorrect procedure callout priority. Expected: %x" " Actual: %x", HWAS::SRCI_PRIORITY_HIGH, l_callout_entry->priority); l_result = 1; break; } } } if(!l_procedure_found) { TS_FAIL("rcTestCalloutProcedure: procedure callout NOT found"); l_result = 2; } } else { TS_FAIL("rcTestCalloutProcedure: No error was returned " "from p9_procedureCallout !!"); l_result = 3; } delete l_errl; l_errl = NULL; FAPI_INF("rcTestCalloutProcedure finished"); return l_result; }
errlHndl_t start_occ(TARGETING::Target * i_target0, TARGETING::Target * i_target1) { errlHndl_t err = NULL; do { const fapi::Target l_fapiTarg0(fapi::TARGET_TYPE_PROC_CHIP, (const_cast<TARGETING::Target*>(i_target0))); fapi::Target l_fapiTarg1; if(i_target1) { l_fapiTarg1.setType(fapi::TARGET_TYPE_PROC_CHIP); l_fapiTarg1.set(const_cast<TARGETING::Target*>(i_target1)); } else { l_fapiTarg1.setType(fapi::TARGET_TYPE_NONE); } FAPI_INVOKE_HWP( err, p8_pm_init, l_fapiTarg0, l_fapiTarg1, PM_CONFIG ); if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"p8_pm_init, config failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // Init path // p8_pm_init.C enum: PM_INIT FAPI_INVOKE_HWP( err, p8_pm_init, l_fapiTarg0, l_fapiTarg1, PM_INIT ); if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"p8_pm_init, init failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } TRACFCOMP( g_fapiTd, INFO_MRK"OCC Finished: p8_pm_init.C enum: PM_INIT" ); //============================== //Start the OCC on primary chip of DCM //============================== FAPI_INVOKE_HWP( err, p8_occ_control, l_fapiTarg0, PPC405_RESET_OFF, PPC405_BOOT_MEM ); if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"occ_control failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } //============================== // Start the OCC on slave chip of DCM //============================== if ( l_fapiTarg1.getType() != fapi::TARGET_TYPE_NONE ) { FAPI_INVOKE_HWP( err, p8_occ_control, l_fapiTarg1, PPC405_RESET_OFF, PPC405_BOOT_MEM ); if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"occ_control failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } } } while(0); return err; }
int executeLoadOCC(uint64_t i_homer_addr_phys, uint64_t i_homer_addr_va, uint64_t i_common_addr_phys, uint64_t i_common_addr_va, uint64_t i_proc_chip) { errlHndl_t err = NULL; int rc = 0; TRACFCOMP( g_fapiTd, "LoadOCC: homer paddr=%016llx vaddr=%016llx. " " common paddr=%016lx vaddr=%016llx. RtProcChip=%llx", i_homer_addr_phys, i_homer_addr_va, i_common_addr_phys, i_common_addr_va, i_proc_chip); do { // Utility to convert i_proc_chip to Target TARGETING::Target* proc_target = NULL; err = RT_TARG::getHbTarget(i_proc_chip, proc_target); if(err) { rc = EINVAL; break; } // Convert to fapi Target fapi::Target fapiTarg( fapi::TARGET_TYPE_PROC_CHIP, (const_cast<TARGETING::Target*>(proc_target) )); TRACFCOMP( g_fapiTd, "FapiTarget: %s",fapiTarg.toEcmdString()); // BAR0 is the Entire HOMER, Bar size is in MB FAPI_INVOKE_HWP( err, p8_pba_bar_config, fapiTarg, 0, //BAR0 i_homer_addr_phys, VMM_HOMER_INSTANCE_SIZE_IN_MB, PBA_CMD_SCOPE_NODAL ); if ( err ) { TRACFCOMP( g_fapiTd, ERR_MRK"Bar0 config failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // BAR1 is what OCC uses to talk to the Centaur. Bar size is in MB uint64_t centaur_addr = proc_target->getAttr<ATTR_IBSCOM_PROC_BASE_ADDR>(); FAPI_INVOKE_HWP( err, p8_pba_bar_config, fapiTarg, 1, //BAR1 centaur_addr, //i_pba_bar_addr //i_pba_bar_size (uint64_t)HBOCC::OCC_IBSCOM_RANGE_IN_MB, PBA_CMD_SCOPE_NODAL ); //i_pba_cmd_scope if ( err != NULL ) { TRACFCOMP( g_fapiTd, ERR_MRK"Bar1 config failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // BAR3 is the OCC Common Area // Bar size is in MB, obtained value of 8MB from Tim Hallett FAPI_INVOKE_HWP( err, p8_pba_bar_config, fapiTarg, 3, //BAR3 i_common_addr_phys, VMM_OCC_COMMON_SIZE_IN_MB, PBA_CMD_SCOPE_NODAL ); if ( err ) { TRACFCOMP( g_fapiTd, ERR_MRK"Bar3 config failed!" ); err->collectTrace(FAPI_TRACE_NAME,256); err->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // Load HOMER image UtilLidMgr lidmgr(HBOCC::OCC_LIDID); size_t lidSize = 0; err = lidmgr.getLidSize(lidSize); if( err ) { break; } err = lidmgr.getLid(reinterpret_cast<void*>(i_homer_addr_va), lidSize); if( err ) { break; } TRACFCOMP( g_fapiTd, "OCC lid loaded. ID:%x size:%d", HBOCC::OCC_LIDID, lidSize); // Setup Host Data area of HOMER err = addHostData(i_homer_addr_va+HOMER_OFFSET_TO_OCC_HOST_DATA); if( err ) { break; } } while(0); if ( err ) { uint64_t status = err->plid(); errlCommit( err, HWPF_COMP_ID ); if(g_hostInterfaces && g_hostInterfaces->report_failure) { g_hostInterfaces->report_failure(status, i_proc_chip); } if(rc == 0) { rc = -1; } } return rc; }
void* call_mss_power_cleanup (void *io_pArgs) { errlHndl_t l_err = NULL; IStepError l_stepError; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_power_cleanup entry" ); TARGETING::TargetHandleList l_mcbistTargetList; getAllChiplets(l_mcbistTargetList, TYPE_MCBIST); for (const auto & l_target : l_mcbistTargetList) { // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_power_cleanup HWP on " "target HUID %.8X", TARGETING::get_huid(l_target)); fapi2::Target <fapi2::TARGET_TYPE_MCBIST> l_fapi_target (l_target); // call the HWP with each fapi2::Target FAPI_INVOKE_HWP(l_err, p9_mss_power_cleanup, l_fapi_target); if (l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: mss_power_cleanup HWP returns error", l_err->reasonCode()); // capture the target data in the elog ErrlUserDetailsTarget(l_target).addToLog(l_err); // Create IStep error log and cross reference to error that // occurred l_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, HWPF_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : mss_power_cleanup HWP( )" ); } } // -- Cumulus only // Get a list of all present Centaurs TargetHandleList l_presCentaurs; getChipResources(l_presCentaurs, TYPE_MEMBUF, UTIL_FILTER_PRESENT); // For each present Centaur for (TargetHandleList::const_iterator l_cenIter = l_presCentaurs.begin(); l_cenIter != l_presCentaurs.end(); ++l_cenIter) { // Make a local copy of the target for ease of use TARGETING::Target * l_pCentaur = *l_cenIter; // Retrieve HUID of current Centaur TARGETING::ATTR_HUID_type l_currCentaurHuid = TARGETING::get_huid(l_pCentaur); // Find all present MBAs associated with this Centaur TARGETING::TargetHandleList l_presMbas; getChildAffinityTargetsByState(l_presMbas, l_pCentaur, CLASS_UNIT, TYPE_MBA, UTIL_FILTER_PRESENT); // If not at least two MBAs found if (l_presMbas.size() < 2) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Not enough MBAs found for Centaur target HUID %.8X, " "skipping this Centaur.", l_currCentaurHuid); continue; } // Cache current MBA HUIDs for tracing TARGETING::ATTR_HUID_type l_currMBA0Huid = TARGETING::get_huid(l_presMbas[0]); TARGETING::ATTR_HUID_type l_currMBA1Huid = TARGETING::get_huid(l_presMbas[1]); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_power_cleanup HWP on " "Centaur HUID %.8X, MBA0 HUID %.8X, " "MBA1 HUID %.8X, ", l_currCentaurHuid, l_currMBA0Huid, l_currMBA1Huid); // Create FAPI Targets. fapi2::Target<fapi2::TARGET_TYPE_MEMBUF_CHIP> l_fapiCentaurTarget( l_pCentaur ); fapi2::Target<fapi2::TARGET_TYPE_MBA_CHIPLET> l_fapiMba0Target( l_presMbas[0] ); fapi2::Target<fapi2::TARGET_TYPE_MBA_CHIPLET> l_fapiMba1Target( l_presMbas[1] ); // Call the HWP with each fapi::Target FAPI_INVOKE_HWP(l_err, p9c_mss_power_cleanup, l_fapiCentaurTarget, l_fapiMba0Target, l_fapiMba1Target); if (l_err) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "mss_power_cleanup HWP failed to perform" " cleanup on centaur: 0x%.8X HWP_ERROR: 0x%.8X", l_currCentaurHuid,l_err->reasonCode()); // Capture the target data in the error log ErrlUserDetailsTarget(l_pCentaur).addToLog(l_err); // Create IStep error log and cross reference error that occurred l_stepError.addErrorDetails(l_err); // Commit error errlCommit(l_err, HWPF_COMP_ID); } else { // Success TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Successfully ran mss_power_cleanup HWP on " "Centaur HUID %.8X, MBA0 HUID %.8X, " "MBA1 HUID %.8X, ", l_currCentaurHuid, l_currMBA0Huid, l_currMBA1Huid); } } TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_power_cleanup exit" ); // end task, returning any errorlogs to IStepDisp return l_stepError.getErrorHandle(); }
/** * @brief Check flash image SHA512 hash value of each explorer chip * and update the flash if it does not match the SHA512 hash * of the image in PNOR. * * @param[out] o_stepError Error handle for logging istep failures * */ void updateAll(IStepError& o_stepError) { bool l_imageLoaded = false; errlHndl_t l_err = nullptr; bool l_rebootRequired = false; // Get a list of OCMB chips TARGETING::TargetHandleList l_ocmbTargetList; getAllChips(l_ocmbTargetList, TYPE_OCMB_CHIP); TRACFCOMP(g_trac_expupd, ENTER_MRK "updateAll: %d ocmb chips found", l_ocmbTargetList.size()); do { // If no OCMB chips exist, we're done. if(l_ocmbTargetList.size() == 0) { break; } // Read explorer fw image from pnor PNOR::SectionInfo_t l_pnorSectionInfo; rawImageInfo_t l_imageInfo; #ifdef CONFIG_SECUREBOOT l_err = PNOR::loadSecureSection(PNOR::OCMBFW); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "updateAll: Failed to load OCMBFW section" " from PNOR!"); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error that occurred o_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, EXPUPD_COMP_ID ); break; } #endif //CONFIG_SECUREBOOT l_imageLoaded = true; // get address and size of packaged image l_err = PNOR::getSectionInfo(PNOR::OCMBFW, l_pnorSectionInfo); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "updateAll: Failure in getSectionInfo()"); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error that occurred o_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, EXPUPD_COMP_ID ); break; } // Verify the header and retrieve address, size and // SHA512 hash of unpackaged image l_err = ocmbFwValidateImage( l_pnorSectionInfo.vaddr, l_pnorSectionInfo.secureProtectedPayloadSize, l_imageInfo); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "updateAll: Failure in expupdValidateImage"); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error that occurred o_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, EXPUPD_COMP_ID ); break; } // For each explorer chip, compare flash hash with PNOR hash and // create a list of explorer chips with differing hash values. TARGETING::TargetHandleList l_flashUpdateList; for(const auto & l_ocmbTarget : l_ocmbTargetList) { sha512regs_t l_regs; //skip all gemini ocmb chips (not updateable) if(l_ocmbTarget->getAttr<TARGETING::ATTR_CHIP_ID>() == POWER_CHIPID::GEMINI_16) { TRACFCOMP(g_trac_expupd, "updateAll: skipping update of gemini OCMB 0x%08x", TARGETING::get_huid(l_ocmbTarget)); continue; } //retrieve the SHA512 hash for the currently flashed image. l_err = getFlashedHash(l_ocmbTarget, l_regs); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "updateAll: Failure in getFlashedHash(huid = 0x%08x)", TARGETING::get_huid(l_ocmbTarget)); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error // that occurred o_stepError.addErrorDetails(l_err); errlCommit(l_err, EXPUPD_COMP_ID); //Don't stop on error, go to next target. continue; } // Trace the hash and image ID values TRACFCOMP(g_trac_expupd, "updateAll: OCMB 0x%08x image ID=0x%08x", TARGETING::get_huid(l_ocmbTarget), l_regs.imageId); TRACFBIN(g_trac_expupd, "SHA512 HASH FROM EXPLORER", l_regs.sha512Hash, HEADER_SHA512_SIZE); //Compare hashes. If different, add to list for update. if(memcmp(l_regs.sha512Hash, l_imageInfo.imageSHA512HashPtr, HEADER_SHA512_SIZE)) { TRACFCOMP(g_trac_expupd, "updateAll: SHA512 hash mismatch on ocmb[0x%08x]", TARGETING::get_huid(l_ocmbTarget)); //add target to our list of targets needing an update l_flashUpdateList.push_back(l_ocmbTarget); } else { TRACFCOMP(g_trac_expupd, "updateAll: SHA512 hash for ocmb[0x%08x]" " matches SHA512 hash of PNOR image.", TARGETING::get_huid(l_ocmbTarget)); } } TRACFCOMP(g_trac_expupd, "updateAll: updating flash for %d OCMB chips", l_flashUpdateList.size()); // update each explorer in the list of chips needing updates for(const auto & l_ocmb : l_flashUpdateList) { TRACFCOMP(g_trac_expupd, "updateAll: updating OCMB 0x%08x", TARGETING::get_huid(l_ocmb)); fapi2::Target<fapi2::TARGET_TYPE_OCMB_CHIP>l_fapi2Target(l_ocmb); // reset watchdog for each ocmb as this function can be very slow INITSERVICE::sendProgressCode(); // Invoke procedure FAPI_INVOKE_HWP(l_err, exp_fw_update, l_fapi2Target, l_imageInfo.imagePtr, l_imageInfo.imageSize); if (l_err) { TRACFCOMP(g_trac_expupd, "Error from exp_fw_update for OCMB 0x%08x", TARGETING::get_huid(l_ocmb)); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error // that occurred o_stepError.addErrorDetails( l_err ); errlCommit(l_err, EXPUPD_COMP_ID); // Don't stop on error, go to next target. continue; } else { TRACFCOMP(g_trac_expupd, "updateAll: successfully updated OCMB 0x%08x", TARGETING::get_huid(l_ocmb)); // Request reboot for new firmware to be used l_rebootRequired = true; } } }while(0); // unload explorer fw image if(l_imageLoaded) { #ifdef CONFIG_SECUREBOOT l_err = PNOR::unloadSecureSection(PNOR::OCMBFW); if(l_err) { TRACFCOMP(g_trac_expupd, ERR_MRK "updateAll: Failed to unload OCMBFW"); l_err->collectTrace(EXPUPD_COMP_NAME); // Create IStep error log and cross reference to error that occurred o_stepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, EXPUPD_COMP_ID ); } #endif //CONFIG_SECUREBOOT } // force reboot if any updates were successful if(l_rebootRequired) { TRACFCOMP(g_trac_expupd, "updateAll: OCMB chip(s) was updated. Requesting reboot..."); Target* l_pTopLevel = nullptr; targetService().getTopLevelTarget( l_pTopLevel ); assert(l_pTopLevel, "expupd::updateAll: no TopLevelTarget"); auto l_reconfigAttr = l_pTopLevel->getAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(); l_reconfigAttr |= RECONFIGURE_LOOP_OCMB_FW_UPDATE; l_pTopLevel->setAttr<TARGETING::ATTR_RECONFIGURE_LOOP>(l_reconfigAttr); } else { TRACFCOMP(g_trac_expupd, "updateAll: No OCMB chips were updated"); } TRACFCOMP(g_trac_expupd, EXIT_MRK"updateAll()"); }
void* call_mss_memdiag (void* io_pArgs) { errlHndl_t errl = nullptr; IStepError l_stepError; TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_memdiag entry"); TARGETING::Target* masterproc = nullptr; TARGETING::targetService().masterProcChipTargetHandle(masterproc); #ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS errl = HBOCC::loadHostDataToSRAM(masterproc, PRDF::ALL_PROC_MEM_MASTER_CORE); assert(nullptr == errl, "Error returned from call to HBOCC::loadHostDataToSRAM"); #endif do { // Actions vary by processor type. ATTR_MODEL_type procType = masterproc->getAttr<ATTR_MODEL>(); if ( MODEL_NIMBUS == procType ) { TargetHandleList trgtList; getAllChiplets( trgtList, TYPE_MCBIST ); // @todo RTC 179458 Intermittent SIMICs action file issues if ( Util::isSimicsRunning() == false ) { // Start Memory Diagnostics. errl = __runMemDiags( trgtList ); if ( nullptr != errl ) break; } for ( auto & tt : trgtList ) { fapi2::Target<fapi2::TARGET_TYPE_MCBIST> ft ( tt ); // Unmask mainline FIRs. FAPI_INVOKE_HWP( errl, mss::unmask::after_memdiags, ft ); if ( nullptr != errl ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss::unmask::after_memdiags(0x%08x) failed", get_huid(tt) ); break; } // Turn off FIFO mode to improve performance. FAPI_INVOKE_HWP( errl, mss::reset_reorder_queue_settings, ft ); if ( nullptr != errl ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "mss::reset_reorder_queue_settings(0x%08x) " "failed", get_huid(tt) ); break; } } if ( nullptr != errl ) break; } else if ( MODEL_CUMULUS == procType ) { TargetHandleList trgtList; getAllChiplets( trgtList, TYPE_MBA ); if ( Util::isSimicsRunning() == false ) { // Start Memory Diagnostics errl = __runMemDiags( trgtList ); if ( nullptr != errl ) break; } // No need to unmask or turn off FIFO. That is already contained // within the other Centaur HWPs. } } while (0); if ( nullptr != errl ) { // Create IStep error log and cross reference to error that occurred l_stepError.addErrorDetails(errl); // Commit Error errlCommit(errl, HWPF_COMP_ID); } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_memdiag exit"); // end task, returning any errorlogs to IStepDisp return l_stepError.getErrorHandle(); }
void axone_dccal_setup(IStepError & io_istepError) { errlHndl_t l_err = nullptr; TargetHandleList l_omic_target_list; getAllChiplets(l_omic_target_list, TYPE_OMIC); for (const auto & l_omic_target : l_omic_target_list) { // call the HWP with each target fapi2::Target<fapi2::TARGET_TYPE_OMIC> l_fapi_omic_target (l_omic_target); TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "p9a_io_omi_scominit HWP target HUID %.8x", get_huid(l_omic_target)); FAPI_INVOKE_HWP(l_err, p9a_io_omi_scominit, l_fapi_omic_target); // process return code. if ( l_err ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9a_io_omi_scominit HWP on target HUID %.8x", l_err->reasonCode(), TARGETING::get_huid(l_omic_target) ); // capture the target data in the elog ErrlUserDetailsTarget(l_omic_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : p9a_io_omi_scominit HWP on target HUID %.8x", TARGETING::get_huid(l_omic_target) ); } TargetHandleList l_omi_target_list; getChildOmiTargetsByState(l_omi_target_list, l_omic_target, CLASS_UNIT, TYPE_OMI, UTIL_FILTER_FUNCTIONAL); uint32_t l_laneVector = 0x00000000; for(const auto & l_omi_target : l_omi_target_list) { // The OMI dc calibration HWP requires us to pass in the OMIC target // and then a bit mask representing which positon of OMI we are calibrating. // To get the position of the OMI relative to its parent OMIC, look up // ATTR_OMI_DL_GROUP_POS then shift the POS_0_VECTOR = 0x000000FF by 1 byte to the left // for every position away from 0 OMI_DL_GROUP_POS is. // Therefore // POS_0_VECTOR = 0x000000FF // POS_1_VECTOR = 0x0000FF00 // POS_2_VECTOR = 0x00FF0000 l_laneVector |= POS_0_VECTOR << (l_omi_target->getAttr<ATTR_OMI_DL_GROUP_POS>() * BITS_PER_BYTE); } TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "p9a_io_omi_dccal HWP target HUID %.8x with lane vector 0x%x", TARGETING::get_huid(l_omic_target), l_laneVector); FAPI_INVOKE_HWP(l_err, p9a_io_omi_dccal, l_fapi_omic_target, l_laneVector); // process return code. if ( l_err ) { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x", l_err->reasonCode(), TARGETING::get_huid(l_omic_target), l_laneVector); // capture the target data in the elog ErrlUserDetailsTarget(l_omic_target).addToLog( l_err ); l_err->collectTrace("ISTEPS_TRACE", 256); // Create IStep error log and cross reference to error that occurred io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : p9a_io_omi_dccal HWP on target HUID %.8x with lane vector 0x%x", TARGETING::get_huid(l_omic_target), l_laneVector ); } } }
void cumulus_dccal_setup(IStepError & io_istepError) { errlHndl_t l_err = nullptr; TARGETING::TargetHandleList l_procTargetList; getAllChips(l_procTargetList, TYPE_PROC); for (const auto & l_proc_target : l_procTargetList) { // a. p9_io_dmi_dccal.C (DMI target) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "p9_io_dmi_dccal HWP target HUID %.8x", TARGETING::get_huid(l_proc_target)); // call the HWP with each target fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi_proc_target (l_proc_target); FAPI_INVOKE_HWP(l_err, p9_io_dmi_dccal, l_fapi_proc_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9_io_dmi_dccal HWP on target HUID %.8x", l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); // capture the target data in the elog ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : p9_io_dmi_dccal HWP on target HUID %.8x", TARGETING::get_huid(l_proc_target) ); } // b. p9_io_cen_dccal.C (Centaur target) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "p9_io_cen_dccal HWP target HUID %.8x", TARGETING::get_huid(l_proc_target)); FAPI_INVOKE_HWP(l_err, p9_io_cen_dccal, l_fapi_proc_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: p9_io_cen_dccal HWP on target HUID %.8x", l_err->reasonCode(), TARGETING::get_huid(l_proc_target) ); // capture the target data in the elog ErrlUserDetailsTarget(l_proc_target).addToLog( l_err ); // Create IStep error log and cross reference to error that occurred io_istepError.addErrorDetails( l_err ); // Commit Error errlCommit( l_err, ISTEP_COMP_ID ); } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS : p9_io_cen_dccal HWP on target HUID %.8x", TARGETING::get_huid(l_proc_target) ); } } }
/** * @brief Execute procedures and steps necessary * to load OCC data in specified processor * * @param[in] i_target Target proc to load * @param[in] i_homerVirtAddrBase Virtual * address of current * proc's HOMER * @param[in] i_homerPhysAddrBase Physical * address of current * proc's HOMER * * @return errlHndl_t Error log image load failed */ errlHndl_t loadOCC(TARGETING::Target* i_target, uint64_t i_homerPhysAddr, uint64_t i_homerVirtAddr, uint64_t i_commonPhysAddr) { errlHndl_t l_errl = NULL; TRACFCOMP( g_fapiTd, ENTER_MRK"loadOCC" ); do{ // Remember where we put things if( i_target ) { i_target->setAttr<ATTR_HOMER_PHYS_ADDR>(i_homerPhysAddr); i_target->setAttr<ATTR_HOMER_VIRT_ADDR>(i_homerVirtAddr); } // cast OUR type of target to a FAPI type of target. const fapi::Target l_fapiTarg(fapi::TARGET_TYPE_PROC_CHIP, (const_cast<Target*>(i_target))); TRACFCOMP( g_fapiTd, "FapiTarget: %s",l_fapiTarg.toEcmdString()); //============================== //Setup for OCC Load //============================== // BAR0 is the Entire HOMER (start of HOMER contains OCC base Image) // Bar size is in MB, obtained value of 4MB from Greg Still TRACUCOMP( g_fapiImpTd, INFO_MRK"loadOCC: OCC Address: 0x%.8X, size=0x%.8X", i_homerPhysAddr, VMM_HOMER_INSTANCE_SIZE_IN_MB); FAPI_INVOKE_HWP( l_errl, p8_pba_bar_config, l_fapiTarg, 0, i_homerPhysAddr, VMM_HOMER_INSTANCE_SIZE_IN_MB, PBA_CMD_SCOPE_NODAL ); if (l_errl) { TRACFCOMP( g_fapiImpTd, ERR_MRK"loadOCC: Bar0 config failed!" ); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // BAR1 is what OCC uses to talk to the Centaur // Bar size is in MB uint64_t centaur_addr = i_target->getAttr<ATTR_IBSCOM_PROC_BASE_ADDR>(); FAPI_INVOKE_HWP( l_errl, p8_pba_bar_config, l_fapiTarg, 1, //i_index centaur_addr, //i_pba_bar_addr (uint64_t)OCC_IBSCOM_RANGE_IN_MB, //i_pba_bar_size PBA_CMD_SCOPE_NODAL ); //i_pba_cmd_scope if ( l_errl ) { TRACFCOMP( g_fapiImpTd, ERR_MRK"loadOCC: Bar1 config failed!" ); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // BAR3 is the OCC Common Area // Bar size is in MB, obtained value of 8MB from Tim Hallett TRACUCOMP( g_fapiImpTd, INFO_MRK"loadOCC: OCC Common Addr: 0x%.8X,size=0x%.8X", i_commonPhysAddr,VMM_OCC_COMMON_SIZE_IN_MB); FAPI_INVOKE_HWP( l_errl, p8_pba_bar_config, l_fapiTarg, 3, i_commonPhysAddr, VMM_OCC_COMMON_SIZE_IN_MB, PBA_CMD_SCOPE_NODAL ); if ( l_errl != NULL ) { TRACFCOMP( g_fapiImpTd, ERR_MRK"loadOCC: Bar3 config failed!" ); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } //============================== //Load the OCC HOMER image //============================== void* occVirt = reinterpret_cast<void *>(i_homerVirtAddr); l_errl = loadOCCImageToHomer( occVirt ); if( l_errl != NULL ) { TRACFCOMP(g_fapiImpTd, ERR_MRK"loadOCC: loadOCCImageToHomer failed!"); break; } }while(0); TRACFCOMP( g_fapiTd, EXIT_MRK"loadOCC"); return l_errl; }
/** * @brief Start OCC for specified DCM pair of processors. * If 2nd input is NULL, OCC will be setup on just * one target. * * @param[in] i_target0: target of first processor in DCM pair * @param[in] i_target1: target of second processor in DCM pair * @param[out] o_failedTarget failed target in case of an error * * @return errlHndl_t Error log of startOCC failed */ errlHndl_t startOCC (Target* i_target0, Target* i_target1, Target *& o_failedTarget) { TRACFCOMP( g_fapiTd, ENTER_MRK"startOCC"); errlHndl_t l_errl = NULL; // cast OUR type of target to a FAPI type of target. // figure out homer offsets const fapi::Target l_fapiTarg0(fapi::TARGET_TYPE_PROC_CHIP, (const_cast<Target*>(i_target0))); fapi::Target l_fapiTarg1; if(i_target1) { l_fapiTarg1.setType(fapi::TARGET_TYPE_PROC_CHIP); l_fapiTarg1.set(const_cast<Target*>(i_target1)); } else { l_fapiTarg1.setType(fapi::TARGET_TYPE_NONE); } do { //============================== // Initialize the logic //============================== // Config path // p8_pm_init.C enum: PM_CONFIG FAPI_INVOKE_HWP( l_errl, p8_pm_init, l_fapiTarg0, l_fapiTarg1, PM_CONFIG ); if ( l_errl != NULL ) { o_failedTarget = i_target0; TRACFCOMP( g_fapiImpTd, ERR_MRK"startOCC: p8_pm_init, config failed!"); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } // Init path // p8_pm_init.C enum: PM_INIT FAPI_INVOKE_HWP( l_errl, p8_pm_init, l_fapiTarg0, l_fapiTarg1, PM_INIT ); if ( l_errl != NULL ) { o_failedTarget = i_target0; TRACFCOMP( g_fapiImpTd, ERR_MRK"startOCC: p8_pm_init, init failed!" ); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } //============================== //Start the OCC on primary chip of DCM //============================== FAPI_INVOKE_HWP( l_errl, p8_occ_control, l_fapiTarg0, PPC405_RESET_OFF, PPC405_BOOT_MEM ); if ( l_errl != NULL ) { o_failedTarget = i_target0; TRACFCOMP( g_fapiImpTd, ERR_MRK"startOCC: occ_control failed!"); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } //============================== // Start the OCC on slave chip of DCM //============================== if ( l_fapiTarg1.getType() != fapi::TARGET_TYPE_NONE ) { FAPI_INVOKE_HWP( l_errl, p8_occ_control, l_fapiTarg1, PPC405_RESET_OFF, PPC405_BOOT_MEM ); if ( l_errl != NULL ) { o_failedTarget = i_target1; TRACFCOMP( g_fapiImpTd, ERR_MRK"startOCCocc_control failed on slave chip!"); l_errl->collectTrace(FAPI_TRACE_NAME,256); l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256); break; } } } while (0); TRACFCOMP( g_fapiTd, EXIT_MRK"startOCC"); return l_errl; }