/* This function is called by the TCP/IP stack when an IP packet should be
* sent. It uses the ethernet ARP module provided by lwIP to resolve the
* destination MAC address. The ARP module will later call our low level
* output function mcf523xfec_output_raw.
*/
err_t
mcf523xfec_output( struct netif * netif, struct pbuf * p, struct ip_addr * ipaddr )
{
err_t res;
mcf523xfec_if_t *fecif = netif->state;
FEC_DEBUG_TX_TIMING( 1 );
/* Make sure only one thread is in this function. */
sys_sem_wait( fecif->tx_sem );
res = etharp_output( netif, ipaddr, p );
FEC_DEBUG_TX_TIMING( 0 );
return res;
}
void
mcf523xfec_reset( mcf523xfec_if_t * fecif )
{
extern void ( *__RAMVEC[] ) ( );
int old_ipl = asm_set_ipl( 7 );
/* Reset the FEC - equivalent to a hard reset */
MCF_FEC_ECR = MCF_FEC_ECR_RESET;
/* Wait for the reset sequence to complete */
while( MCF_FEC_ECR & MCF_FEC_ECR_RESET );
/* Disable all FEC interrupts by clearing the EIMR register */
MCF_FEC_EIMR = 0;
/* Clear any interrupts by setting all bits in the EIR register */
MCF_FEC_EIR = 0xFFFFFFFFUL;
/* Configure Interrupt vectors. */
__RAMVEC[MCF_FEC_VEC_RXF] = mcf523xfec_rx_irq;
/* Set the source address for the controller */
MCF_FEC_PALR =
( fecif->self->addr[0] << 24U ) | ( fecif->self->addr[1] << 16U ) |
( fecif->self->addr[2] << 8U ) | ( fecif->self->addr[3] << 0U );
MCF_FEC_PAUR = ( fecif->self->addr[4] << 24U ) | ( fecif->self->addr[5] << 16U );
/* Initialize the hash table registers */
MCF_FEC_IAUR = 0;
MCF_FEC_IALR = 0;
/* Set Receive Buffer Size */
#if RX_BUFFER_SIZE != 2048
#error "RX_BUFFER_SIZE must be set to 2048 for safe FEC operation."
#endif
MCF_FEC_EMRBR = RX_BUFFER_SIZE - 1;
/* Point to the start of the circular Rx buffer descriptor queue */
MCF_FEC_ERDSR = nbuf_get_start( NBUF_RX );
/* Point to the start of the circular Tx buffer descriptor queue */
MCF_FEC_ETDSR = nbuf_get_start( NBUF_TX );
/* Set the tranceiver interface to MII mode */
MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL( MCF_FEC_MTU ) | MCF_FEC_RCR_MII_MODE;
/* Set MII Speed Control Register for 2.5Mhz */
MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( FSYS_2 / ( 2UL * 2500000UL ) );
/* Only operate in half-duplex, no heart beat control */
MCF_FEC_TCR = 0;
/* Enable Debug support */
FEC_DEBUG_INIT;
FEC_DEBUG_RX_TIMING( 0 );
FEC_DEBUG_TX_TIMING( 0 );
( void )asm_set_ipl( old_ipl );
}
/**
* Reset MAC controller
*
* @param MAC controller descriptor
* @return none
*/
void
MAC_Reset( mcf5xxxfec_if_t * fecif )
{
portENTER_CRITICAL();
/* Set the source address for the controller */
FEC_ResetProcessing(fecif->self->addr);
/* Enable Debug support */
FEC_DEBUG_INIT;
FEC_DEBUG_RX_TIMING( 0 );
FEC_DEBUG_TX_TIMING( 0 );
portEXIT_CRITICAL();
}
