static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
struct cpuidle_state *state)
{
/* 20100907 race condition fix [START] */
//void __iomem *flow_ctrl = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE);
void __iomem *flow_ctrl;
ktime_t enter, exit;
s64 us;
//u32 reg = FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME;
u32 reg;
//flow_ctrl = flow_ctrl + FLOW_CTRL_HALT_CPUx_EVENTS(dev->cpu);
local_irq_disable();
flow_ctrl = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + FLOW_CTRL_HALT_CPUx_EVENTS(dev->cpu);
reg = FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME;
/* 20100907 race condition fix [END] */
smp_rmb();
enter = ktime_get();
if (!need_resched()) {
__raw_writel(reg, flow_ctrl);
reg = __raw_readl(flow_ctrl);
dsb();
__asm__ volatile ("wfi");
__raw_writel(0, flow_ctrl);
reg = __raw_readl(flow_ctrl);
}
static
void zynq_cpu1_init(void)
{
#if 0
unsigned long r;
unsigned long orig_reset;
unsigned long loop;
unsigned long ctrl;
/* Initialize Snoop Control Unit */
ctrl = mmio_readl(ZYNQ_SCU_PHYS_BASE + SCU_CONTROL_0);
ctrl |= 1;
mmio_writel(ctrl, ZYNQ_SCU_PHYS_BASE + SCU_CONTROL_0);
/* Set boot entry */
mmio_writel(virt_to_phys(secondary_startup),
IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + EVP_CPU_RESET_VECTOR_0);
dsb();
isb();
/* Halt CPU */
mmio_writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + FLOW_CTRL_HALT_CPUx_EVENTS(1));
dsb();
isb();
/* CPU Clock Stop */
r = mmio_readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0);
r &= ~CPU_CLK_STOP(1);
mmio_writel(r, IO_ADDRESS(TEGRA_CLK_RESET_BASE) + CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0);
dsb();
isb();
/* Restart Slave CPU */
mmio_writel(CPU_RESET(1), IO_ADDRESS(TEGRA_CLK_RESET_BASE) + CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0);
dsb();
isb();
#endif
}
