PNAME(audio0_p) = { "fin_pll", "cdclk0", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; PNAME(audio1_p) = { "fin_pll", "cdclk1", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; PNAME(audio2_p) = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2", "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" }; PNAME(hdmi_p) = { "dout_hdmi_pixel", "sclk_hdmiphy" }; PNAME(maudio0_p) = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll", "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = { FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = { FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), FRATE(none, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), }; static struct samsung_fixed_factor_clock exynos5420_fixed_factor_clks[] __initdata = { FFACTOR(none, "sclk_hsic_12m", "fin_pll", 1, 2, 0), };
"sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", "sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", "sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; /* fixed rate clocks generated outside the soc */ struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), }; struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), }; /* list of mux clocks supported in all exynos4 soc's */
FFACTOR(0, "upll_3", "upll", 1, 3, 0), }; PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" }; static struct samsung_mux_clock s3c2442_muxes[] __initdata = { MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2), }; /* * fixed rate clocks generated outside the soc * Only necessary until the devicetree-move is complete */ #define XTI 1 static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = { FRATE(XTI, "xti", NULL, 0, 0), }; static void __init s3c2410_common_clk_register_fixed_ext( struct samsung_clk_provider *ctx, unsigned long xti_f) { struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal"); s3c2410_common_frate_clks[0].fixed_rate = xti_f; samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks, ARRAY_SIZE(s3c2410_common_frate_clks)); samsung_clk_register_alias(ctx, &xti_alias, 1); }
MUX(MOUT_MMC2, "mout_mmc2", mout_group2_6442_p, CLK_SRC4, 8, 4), MUX(MOUT_MMC1, "mout_mmc1", mout_group2_6442_p, CLK_SRC4, 4, 4), MUX(MOUT_MMC0, "mout_mmc0", mout_group2_6442_p, CLK_SRC4, 0, 4), MUX(MOUT_PWM, "mout_pwm", mout_group2_6442_p, CLK_SRC5, 12, 4), MUX(MOUT_SPI0, "mout_spi0", mout_group2_6442_p, CLK_SRC5, 0, 4), MUX(MOUT_AUDIO1, "mout_audio1", mout_audio1_6442_p, CLK_SRC6, 4, 4), MUX(MOUT_AUDIO0, "mout_audio0", mout_audio0_6442_p, CLK_SRC6, 0, 4), MUX(MOUT_CLKSEL, "mout_clksel", mout_clksel_6442_p, CLK_OUT, 12, 5), }; /* S5PV210-specific fixed rate clocks generated inside the SoC. */ static struct samsung_fixed_rate_clock s5pv210_frate_clks[] __initdata = { FRATE(SCLK_HDMI27M, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), FRATE(SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), FRATE(SCLK_USBPHY1, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), }; /* S5P6442-specific fixed rate clocks generated inside the SoC. */ static struct samsung_fixed_rate_clock s5p6442_frate_clks[] __initdata = { FRATE(SCLK_USBPHY0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 30000000), }; /* Common clock dividers. */ static struct samsung_div_clock div_clks[] __initdata = { DIV(DOUT_PCLKP, "dout_pclkp", "dout_hclkp", CLK_DIV0, 28, 3), DIV(DOUT_PCLKD, "dout_pclkd", "dout_hclkd", CLK_DIV0, 20, 3), DIV(DOUT_A2M, "dout_a2m", "mout_apll", CLK_DIV0, 4, 3),
"mout_mpll_user", "mout_epll", "mout_vpll", "mout_cpll", "none", "none", "none", "none", "none", "none" }; PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "fin_pll", "mout_mpll_user", "mout_epll", "mout_vpll", "mout_cpll", "none", "none", "none", "none", "none", "none" }; PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", "spdif_extclk" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0), }; /* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000), FRATE(0, "sclk_hdmi27m", NULL, 0, 27000000), FRATE(0, "sclk_dptxphy", NULL, 0, 24000000), FRATE(0, "sclk_uhostphy", NULL, 0, 48000000), }; static struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(0, "fout_mplldiv2", "fout_mpll", 1, 2, 0), FFACTOR(0, "fout_bplldiv2", "fout_bpll", 1, 2, 0), };
/* * List of parent clocks for Muxes in CMU_FSYS0 */ PNAME(mout_aclk_fsys0_200_user_p) = { "fin_pll", "aclk_fsys0_200" }; PNAME(mout_sclk_mmc2_user_p) = { "fin_pll", "sclk_mmc2" }; PNAME(mout_sclk_usbdrd300_user_p) = { "fin_pll", "sclk_usbdrd300" }; PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_phyclock" }; PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_pipe_pclk" }; /* fixed rate clocks used in the FSYS0 block */ static struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, 0, 60000000), FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, 0, 125000000), }; static unsigned long fsys0_clk_regs[] __initdata = { MUX_SEL_FSYS00, MUX_SEL_FSYS01, MUX_SEL_FSYS02, ENABLE_ACLK_FSYS00, ENABLE_ACLK_FSYS01, ENABLE_SCLK_FSYS01, ENABLE_SCLK_FSYS02, ENABLE_SCLK_FSYS04, }; static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
/* * List of parent clocks for Muxes in CMU_FSYS0 */ PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" }; PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" }; PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" }; PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_phyclock" }; PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll", "phyclk_usbdrd300_udrd30_pipe_pclk" }; /* fixed rate clocks used in the FSYS0 block */ struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = { FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL, CLK_IS_ROOT, 60000000), FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL, CLK_IS_ROOT, 125000000), }; static unsigned long fsys0_clk_regs[] __initdata = { MUX_SEL_FSYS00, MUX_SEL_FSYS01, MUX_SEL_FSYS02, ENABLE_ACLK_FSYS00, ENABLE_ACLK_FSYS01, ENABLE_SCLK_FSYS01, ENABLE_SCLK_FSYS02, ENABLE_SCLK_FSYS04, };
/* S3C6400-specific parent clocks. */ PNAME(scaler_lcd_p6400) = { "mout_epll", "dout_mpll", "none", "none" }; PNAME(irda_p6400) = { "mout_epll", "dout_mpll", "none", "clk48m" }; PNAME(uhost_p6400) = { "clk48m", "mout_epll", "dout_mpll", "none" }; /* S3C6410-specific parent clocks. */ PNAME(clk27_p6410) = { "clk27m", "fin_pll" }; PNAME(scaler_lcd_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "none" }; PNAME(irda_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "clk48m" }; PNAME(uhost_p6410) = { "clk48m", "mout_epll", "dout_mpll", "fin_pll" }; PNAME(audio2_p6410) = { "mout_epll", "dout_mpll", "fin_pll", "iiscdclk2", "pcmcdclk1", "none", "none", "none" }; /* Fixed rate clocks generated outside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_ext_clks) __initdata = { FRATE(0, "fin_pll", NULL, CLK_IS_ROOT, 0), FRATE(0, "xusbxti", NULL, CLK_IS_ROOT, 0), }; /* Fixed rate clocks generated inside the SoC. */ FIXED_RATE_CLOCKS(s3c64xx_fixed_rate_clks) __initdata = { FRATE(CLK27M, "clk27m", NULL, CLK_IS_ROOT, 27000000), FRATE(CLK48M, "clk48m", NULL, CLK_IS_ROOT, 48000000), }; /* List of clock muxes present on all S3C64xx SoCs. */ MUX_CLOCKS(s3c64xx_mux_clks) __initdata = { MUX_F(0, "mout_syncmux", hclkx2_p, OTHERS, 6, 1, 0, CLK_MUX_READ_ONLY), MUX(MOUT_APLL, "mout_apll", apll_p, CLK_SRC, 0, 1), MUX(MOUT_MPLL, "mout_mpll", mpll_p, CLK_SRC, 1, 1), MUX(MOUT_EPLL, "mout_epll", epll_p, CLK_SRC, 2, 1),
none, xtal, arm_clk, spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata, usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o, b_200_o, sata_o, usb_o, gmac0_o, cs250_o, nr_clks, }; /* parent clock name list */ PNAME(mout_armclk_p) = { "cplla", "cpllb" }; PNAME(mout_spi_p) = { "div125", "div200" }; /* fixed rate clocks generated outside the soc */ struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks */ struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000), FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), }; /* fixed factor clocks */ struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { FFACTOR(none, "div250", "ppll", 1, 4, 0), FFACTOR(none, "div200", "ppll", 1, 5, 0),
PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll", "mout_sclk_mpll", "ff_dout_spll2" }; PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" }; PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" }; PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" }; PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" }; PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" }; PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5x_fixed_rate_ext_clks[] __initdata = { FRATE(CLK_FIN_PLL, "fin_pll", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initdata = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), FRATE(0, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000), FRATE(0, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000), FRATE(0, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000), FRATE(0, "sclk_usbh20_scan_clk", NULL, CLK_IS_ROOT, 480000000), }; static struct samsung_fixed_factor_clock exynos5x_fixed_factor_clks[] __initdata = { FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0), FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
"sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll" }; PNAME(mout_audio1_p4x12) = { "cdclk1", "none", "sclk_hdmi24m", "sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; PNAME(mout_audio2_p4x12) = { "cdclk2", "none", "sclk_hdmi24m", "sclk_usbphy0", "xxti", "xusbxti", "mout_mpll_user_t", "sclk_epll", "sclk_vpll", }; PNAME(aclk_p4412) = { "mout_mpll_user_t", "sclk_apll", }; PNAME(mout_user_aclk400_mcuisp_p4x12) = {"fin_pll", "div_aclk400_mcuisp", }; PNAME(mout_user_aclk200_p4x12) = {"fin_pll", "div_aclk200", }; PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), }; static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), }; /* list of mux clocks supported in all exynos4 soc's */
PNAME(mout_g3d_p) = { "mout_g3d_0", "mout_g3d_1" }; PNAME(mout_jpeg_p) = { "mout_jpeg_0", "mout_jpeg_1" }; PNAME(mout_jpeg1_p) = { "mout_epll", "mout_g3d_pll" }; PNAME(group_aclk_isp0_300_p) = { "mout_isp_pll", "div_mpll_pre" }; PNAME(group_aclk_isp0_400_user_p) = { "fin_pll", "div_aclk_400_mcuisp" }; PNAME(group_aclk_isp0_300_user_p) = { "fin_pll", "mout_aclk_isp0_300" }; PNAME(group_aclk_isp1_300_user_p) = { "fin_pll", "mout_aclk_isp1_300" }; PNAME(group_mout_mpll_user_t_p) = { "mout_mpll_user_t" }; static struct samsung_fixed_factor_clock exynos4415_fixed_factor_clks[] __initdata = { /* HACK: fin_pll hardcoded to xusbxti until detection is implemented. */ FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0), }; static struct samsung_fixed_rate_clock exynos4415_fixed_rate_clks[] __initdata = { FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), }; static struct samsung_mux_clock exynos4415_mux_clks[] __initdata = { /* * NOTE: Following table is sorted by register address in ascending * order and then bitfield shift in descending order, as it is done * in the User's Manual. When adding new entries, please make sure * that the order is preserved, to avoid merge conflicts and make * further work with defined data easier. */ /* SRC_LEFTBUS */ MUX(CLK_MOUT_MPLL_USER_L, "mout_mpll_user_l", mout_mpll_user_p, SRC_LEFTBUS, 4, 1), MUX(CLK_MOUT_GDL, "mout_gdl", mout_gdl_p, SRC_LEFTBUS, 0, 1),
"sclk_mpll_user", "sclk_epll", "sclk_vpll", "sclk_cpll" }; PNAME(mout_audio1_p) = { "cdclk1", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "sclk_mpll_user", "sclk_epll", "sclk_vpll", "sclk_cpll" }; PNAME(mout_audio2_p) = { "cdclk2", "fin_pll", "sclk_hdmi27m", "sclk_dptxphy", "sclk_uhostphy", "sclk_hdmiphy", "sclk_mpll_user", "sclk_epll", "sclk_vpll", "sclk_cpll" }; PNAME(mout_spdif_p) = { "sclk_audio0", "sclk_audio1", "sclk_audio2", "spdif_extclk" }; /* fixed rate clocks generated outside the soc */ struct samsung_fixed_rate_clock exynos5250_fixed_rate_ext_clks[] __initdata = { FRATE(fin_pll, "fin_pll", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ struct samsung_fixed_rate_clock exynos5250_fixed_rate_clks[] __initdata = { FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_hdmi27m", NULL, CLK_IS_ROOT, 27000000), FRATE(none, "sclk_dptxphy", NULL, CLK_IS_ROOT, 24000000), FRATE(none, "sclk_uhostphy", NULL, CLK_IS_ROOT, 48000000), }; struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(none, "fout_mplldiv2", "fout_mpll", 1, 2, 0), FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), };