void FTM_SetupQuadDecode(FTM_Type *base,
const ftm_phase_params_t *phaseAParams,
const ftm_phase_params_t *phaseBParams,
ftm_quad_decode_mode_t quadMode)
{
assert(phaseAParams);
assert(phaseBParams);
uint32_t reg;
/* Set Phase A filter value if phase filter is enabled */
if (phaseAParams->enablePhaseFilter)
{
reg = base->FILTER;
reg &= ~(FTM_FILTER_CH0FVAL_MASK);
reg |= FTM_FILTER_CH0FVAL(phaseAParams->phaseFilterVal);
base->FILTER = reg;
}
/* Set Phase B filter value if phase filter is enabled */
if (phaseBParams->enablePhaseFilter)
{
reg = base->FILTER;
reg &= ~(FTM_FILTER_CH1FVAL_MASK);
reg |= FTM_FILTER_CH1FVAL(phaseBParams->phaseFilterVal);
base->FILTER = reg;
}
/* Set Quadrature decode properties */
reg = base->QDCTRL;
reg &= ~(FTM_QDCTRL_QUADMODE_MASK | FTM_QDCTRL_PHAFLTREN_MASK | FTM_QDCTRL_PHBFLTREN_MASK | FTM_QDCTRL_PHAPOL_MASK |
FTM_QDCTRL_PHBPOL_MASK);
reg |= (FTM_QDCTRL_QUADMODE(quadMode) | FTM_QDCTRL_PHAFLTREN(phaseAParams->enablePhaseFilter) |
FTM_QDCTRL_PHBFLTREN(phaseBParams->enablePhaseFilter) | FTM_QDCTRL_PHAPOL(phaseAParams->phasePolarity) |
FTM_QDCTRL_PHBPOL(phaseBParams->phasePolarity));
base->QDCTRL = reg;
/* Enable Quad decode */
base->QDCTRL |= FTM_QDCTRL_QUADEN_MASK;
}
void Qd::setMode ()
{
//===Setings pin===//
//pha
pha.settingPinPort(QdDef::PhaPort);
pha.settingPin(QdDef::PhaPin, QdDef::PhaAlt);
//phb
phb.settingPinPort(QdDef::PhbPort);
phb.settingPin(QdDef::PhbPin, QdDef::PhbAlt);
//===Settings timer===//
FTM_SC_REG(ftm_ptr[num_ftm]) = 0;
setPeriod(FTM_MOD_MOD_MASK);
setInitValue(0);
FTM_MODE_REG (ftm_ptr[num_ftm]) |= FTM_MODE_WPDIS_MASK;
FTM_MODE_REG (ftm_ptr[num_ftm]) |= FTM_MODE_FTMEN_MASK;
FTM_CnSC_REG(ftm_ptr[num_ftm], 0) = 0;
FTM_CnSC_REG(ftm_ptr[num_ftm], 1) = 0;
FTM_QDCTRL_REG(ftm_ptr[num_ftm]) |= FTM_QDCTRL_QUADEN_MASK|FTM_QDCTRL_PHAFLTREN_MASK|FTM_QDCTRL_PHBFLTREN_MASK;
FTM_FILTER_REG (ftm_ptr[num_ftm]) |= FTM_FILTER_CH0FVAL(2) | FTM_FILTER_CH1FVAL(2) ;
start ();
}
