/** * lapic_get_maxlvt - get the maximum number of local vector table entries */ int lapic_get_maxlvt(void) { unsigned int v = apic_read(APIC_LVR); /* 82489DXs do not report # of LVT entries. */ return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; }
/** * lapic_get_maxlvt - get the maximum number of local vector table entries */ int lapic_get_maxlvt(void) { unsigned int v, maxlvt; v = apic_read(APIC_LVR); maxlvt = GET_APIC_MAXLVT(v); return maxlvt; }
int lapic_get_maxlvt(void) { unsigned int v; v = apic_read(APIC_LVR); return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; }
int get_maxlvt(void) { unsigned int v, ver, maxlvt; v = apic_read(APIC_LVR); ver = GET_APIC_VERSION(v); maxlvt = GET_APIC_MAXLVT(v); return maxlvt; }
int get_maxlvt(void) { unsigned int v, ver, maxlvt; v = apic_read(APIC_LVR); ver = GET_APIC_VERSION(v); /* 82489DXs do not report # of LVT entries. */ maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; return maxlvt; }
/** * lapic_get_maxlvt - get the maximum number of local vector table entries */ int lapic_get_maxlvt(void) { unsigned int v; v = apic_read(APIC_LVR); /* * - we always have APIC integrated on 64bit mode * - 82489DXs do not report # of LVT entries */ return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; }
void enable_local_APIC(void) { unsigned long value; // Clear the logical destination ID value = apic_read(APIC_LDR); value &= 0x00ffffff; // Dest = 0 apic_write(APIC_LDR, value); /* Set Task Priority to 'accept all' */ value = apic_read(APIC_TASKPRI); value &= 0xffffff00; apic_write(APIC_TASKPRI, value); // bring the APIC into flat delivery mode. value = apic_read(APIC_DFR); value |= 0xf0000000; // bits 28-31 = 1111 -> flat mode apic_write(APIC_DFR, value); /* now enable APIC */ value = apic_read(APIC_SPIV); value |= (1 << 8); /* Enable APIC (bit==1) */ // value &= ~(1<<9); /* Enable focus processor (bit==0) */ value |= (1 << 9); /* Disable focus processor (bit==1) */ value |= SPURIOUS_APIC_VECTOR; /* Set spurious IRQ vector to 0xff */ apic_write(APIC_SPIV, value); /* setup LVTERR on integrated APICs */ if ((lapic_version[get_processor_id()] & 0xF0) != APIC_VER_82489DX) { /* !82489DX */ unsigned int value, maxlvt; maxlvt = GET_APIC_MAXLVT(apic_read(APIC_VERSION)); if (maxlvt > 3) apic_write(APIC_ESR, 0); value = apic_read(APIC_ESR); /*smp_debug_printf(SMP_DEBUG_ALL, "ESR value before enabling vector: %08lx\n", value); */ value = ERROR_APIC_VECTOR; apic_write(APIC_LVERR, value); /* clear errors after enabling vector */ if (maxlvt > 3) apic_write(APIC_ESR, 0); value = apic_read(APIC_ESR); /*smp_debug_printf(SMP_DEBUG_ALL, "ESR value after enabling vector: %08lx\n", value); */ } else /*smp_debug_printf(SMP_DEBUG_ALL, "No ESR for 82489DX.\n"); */ ; }
static int __init enable_apic(void) { uint msr_low, msr_high; uint val; /* enable local APIC via MSR. Forgetting this is a fun way to * lock the box. But we have to hope this is allowed if the APIC * has already been enabled. * * IA32 V3, 7.4.2 */ rdmsr(MSR_IA32_APICBASE, msr_low, msr_high); if ((msr_low & (1 << 11)) == 0) wrmsr(MSR_IA32_APICBASE, msr_low | (1<<11), msr_high); /* even if the apic is up we must check for a good APIC */ /* IA32 V3, 7.4.15 */ val = apic_read(APIC_LVR); if (!APIC_INTEGRATED(GET_APIC_VERSION(val))) goto not_local_apic; /* LVT0,LVT1,LVTT,LVTPC */ if (GET_APIC_MAXLVT(apic_read(APIC_LVR)) < 4) goto not_local_apic; /* IA32 V3, 7.4.14.1 */ val = apic_read(APIC_SPIV); if (!(val & APIC_SPIV_APIC_ENABLED)) apic_write(APIC_SPIV, val | APIC_SPIV_APIC_ENABLED); return !!(val & APIC_SPIV_APIC_ENABLED); not_local_apic: /* disable the apic only if it was disabled */ if ((msr_low & (1 << 11)) == 0) wrmsr(MSR_IA32_APICBASE, msr_low & ~(1<<11), msr_high); printk(KERN_ERR "oprofile: no suitable local APIC. Falling back to RTC mode.\n"); return -ENODEV; }
int get_maxlvt(void) { unsigned int v = apic_read(APIC_LVR); return GET_APIC_MAXLVT(v); }
/** * Prints various local APIC registers of interest to the console. */ void lapic_dump(void) { char buf[128]; printk(KERN_DEBUG "LOCAL APIC DUMP (LOGICAL CPU #%d):\n", this_cpu); /* * Lead off with the important stuff... */ printk(KERN_DEBUG " ID: 0x%08x (id=%d)\n", apic_read(APIC_ID), GET_APIC_ID(apic_read(APIC_ID)) ); printk(KERN_DEBUG " VER: 0x%08x (version=0x%x, max_lvt=%d)\n", apic_read(APIC_LVR), GET_APIC_VERSION(apic_read(APIC_LVR)), GET_APIC_MAXLVT(apic_read(APIC_LVR)) ); printk(KERN_DEBUG " ESR: 0x%08x (Error Status Reg, non-zero is bad)\n", apic_read(APIC_ESR) ); printk(KERN_DEBUG " SVR: 0x%08x (Spurious vector=%d, %s)\n", apic_read(APIC_SPIV), apic_read(APIC_SPIV) & APIC_VECTOR_MASK, (apic_read(APIC_SPIV) & APIC_SPIV_APIC_ENABLED) ? "APIC IS ENABLED" : "APIC IS DISABLED" ); /* * Local Vector Table */ printk(KERN_DEBUG " Local Vector Table Entries:\n"); printk(KERN_DEBUG " LVT[0] Timer: 0x%08x (%s)\n", apic_read(APIC_LVTT), lvt_stringify(apic_read(APIC_LVTT), buf) ); printk(KERN_DEBUG " LVT[1] Thermal: 0x%08x (%s)\n", apic_read(APIC_LVTTHMR), lvt_stringify(apic_read(APIC_LVTTHMR), buf) ); printk(KERN_DEBUG " LVT[2] Perf Cnt: 0x%08x (%s)\n", apic_read(APIC_LVTPC), lvt_stringify(apic_read(APIC_LVTPC), buf) ); printk(KERN_DEBUG " LVT[3] LINT0 Pin: 0x%08x (%s)\n", apic_read(APIC_LVT0), lvt_stringify(apic_read(APIC_LVT0), buf) ); printk(KERN_DEBUG " LVT[4] LINT1 Pin: 0x%08x (%s)\n", apic_read(APIC_LVT1), lvt_stringify(apic_read(APIC_LVT1), buf) ); printk(KERN_DEBUG " LVT[5] Error: 0x%08x (%s)\n", apic_read(APIC_LVTERR), lvt_stringify(apic_read(APIC_LVTERR), buf) ); /* * APIC timer configuration registers */ printk(KERN_DEBUG " Local APIC Timer:\n"); printk(KERN_DEBUG " DCR (Divide Config Reg): 0x%08x\n", apic_read(APIC_TDCR) ); printk(KERN_DEBUG " ICT (Initial Count Reg): 0x%08x\n", apic_read(APIC_TMICT) ); printk(KERN_DEBUG " CCT (Current Count Reg): 0x%08x\n", apic_read(APIC_TMCCT) ); /* * Logical APIC addressing mode registers */ printk(KERN_DEBUG " Logical Addressing Mode Information:\n"); printk(KERN_DEBUG " LDR (Logical Dest Reg): 0x%08x (id=%d)\n", apic_read(APIC_LDR), GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)) ); printk(KERN_DEBUG " DFR (Dest Format Reg): 0x%08x (%s)\n", apic_read(APIC_DFR), (apic_read(APIC_DFR) == APIC_DFR_FLAT) ? "FLAT" : "CLUSTER" ); /* * Task/processor/arbitration priority registers */ printk(KERN_DEBUG " Task/Processor/Arbitration Priorities:\n"); printk(KERN_DEBUG " TPR (Task Priority Reg): 0x%08x\n", apic_read(APIC_TASKPRI) ); printk(KERN_DEBUG " PPR (Processor Priority Reg): 0x%08x\n", apic_read(APIC_PROCPRI) ); printk(KERN_DEBUG " APR (Arbitration Priority Reg): 0x%08x\n", apic_read(APIC_ARBPRI) ); }
/** * Returns the number of entries in the Local Vector Table minus one. * * This should return 5 or higher on all x86_64 CPUs. * 6 is returned if the APIC Thermal Interrupt is supported, 5 otherwise. */ static uint32_t lapic_get_maxlvt(void) { return GET_APIC_MAXLVT(apic_read(APIC_LVR)); }