SI iq2000bf_h_gr_get (SIM_CPU *current_cpu, UINT regno) { return GET_H_GR (regno); }
SI crisv10f_h_gr_get (SIM_CPU *current_cpu, UINT regno) { return GET_H_GR (regno); }
BI frvbf_check_non_excepting_load ( SIM_CPU *current_cpu, SI base_index, SI disp_index, SI target_index, SI immediate_disp, QI data_size, BI is_float ) { BI rc = 1; /* perform the load. */ SIM_DESC sd = CPU_STATE (current_cpu); int daec = 0; int rec = 0; int ec = 0; USI necr; int do_elos; SI NE_flags[2]; SI NE_base; SI nesr; SI ne_index; FRV_REGISTER_CONTROL *control; SI address = GET_H_GR (base_index); if (disp_index >= 0) address += GET_H_GR (disp_index); else address += immediate_disp; /* Check for interrupt factors. */ switch (data_size) { case NESR_UQI_SIZE: case NESR_QI_SIZE: break; case NESR_UHI_SIZE: case NESR_HI_SIZE: if (address & 1) ec = 1; break; case NESR_SI_SIZE: if (address & 3) ec = 1; break; case NESR_DI_SIZE: if (address & 7) ec = 1; if (target_index & 1) rec = 1; break; case NESR_XI_SIZE: if (address & 0xf) ec = 1; if (target_index & 3) rec = 1; break; default: { IADDR pc = GET_H_PC (); sim_engine_abort (sd, current_cpu, pc, "check_non_excepting_load: Incorrect data_size\n"); break; } } control = CPU_REGISTER_CONTROL (current_cpu); if (control->spr[H_SPR_NECR].implemented) { necr = GET_NECR (); do_elos = GET_NECR_VALID (necr) && GET_NECR_ELOS (necr); } else do_elos = 0; /* NECR, NESR, NEEAR are only implemented for the full frv machine. */ if (do_elos) { ne_index = next_available_nesr (current_cpu, NO_NESR); if (ne_index == NO_NESR) { IADDR pc = GET_H_PC (); sim_engine_abort (sd, current_cpu, pc, "No available NESR register\n"); } /* Fill in the basic fields of the NESR. */ nesr = GET_NESR (ne_index); SET_NESR_VALID (nesr); SET_NESR_EAV (nesr); SET_NESR_DRN (nesr, target_index); SET_NESR_SIZE (nesr, data_size); SET_NESR_NEAN (nesr, ne_index); if (is_float) SET_NESR_FR (nesr); else CLEAR_NESR_FR (nesr); /* Set the corresponding NEEAR. */ SET_NEEAR (ne_index, address); SET_NESR_DAEC (nesr, 0); SET_NESR_REC (nesr, 0); SET_NESR_EC (nesr, 0); } /* Set the NE flag corresponding to the target register if an interrupt factor was detected. daec is not checked here yet, but is declared for future reference. */ if (is_float) NE_base = H_SPR_FNER0; else NE_base = H_SPR_GNER0; GET_NE_FLAGS (NE_flags, NE_base); if (rec) { SET_NE_FLAG (NE_flags, target_index); if (do_elos) SET_NESR_REC (nesr, NESR_REGISTER_NOT_ALIGNED); } if (ec) { SET_NE_FLAG (NE_flags, target_index); if (do_elos) SET_NESR_EC (nesr, NESR_MEM_ADDRESS_NOT_ALIGNED); } if (do_elos) SET_NESR (ne_index, nesr); /* If no interrupt factor was detected then set the NE flag on the target register if the NE flag on one of the input registers is already set. */ if (! rec && ! ec && ! daec) { BI ne_flag = GET_NE_FLAG (NE_flags, base_index); if (disp_index >= 0) ne_flag |= GET_NE_FLAG (NE_flags, disp_index); if (ne_flag) { SET_NE_FLAG (NE_flags, target_index); rc = 0; /* Do not perform the load. */ } else CLEAR_NE_FLAG (NE_flags, target_index); } SET_NE_FLAGS (NE_base, NE_flags); return rc; /* perform the load? */ }
void frvbf_check_recovering_store ( SIM_CPU *current_cpu, PCADDR address, SI regno, int size, int is_float ) { FRV_CACHE *cache = CPU_DATA_CACHE (current_cpu); int reg_ix; CPU_RSTR_INVALIDATE(current_cpu) = 0; for (reg_ix = next_valid_nesr (current_cpu, NO_NESR); reg_ix != NO_NESR; reg_ix = next_valid_nesr (current_cpu, reg_ix)) { if (address == GET_H_SPR (H_SPR_NEEAR0 + reg_ix)) { SI nesr = GET_NESR (reg_ix); int nesr_drn = GET_NESR_DRN (nesr); BI nesr_fr = GET_NESR_FR (nesr); SI remain; /* Invalidate cache block containing this address. If we need to count cycles, then the cache operation will be initiated from the model profiling functions. See frvbf_model_.... */ if (model_insn) { CPU_RSTR_INVALIDATE(current_cpu) = 1; CPU_LOAD_ADDRESS (current_cpu) = address; } else frv_cache_invalidate (cache, address, 1/* flush */); /* Copy the stored value to the register indicated by NESR.DRN. */ for (remain = size; remain > 0; remain -= 4) { SI value; if (is_float) value = GET_H_FR (regno); else value = GET_H_GR (regno); switch (size) { case 1: value &= 0xff; break; case 2: value &= 0xffff; break; default: break; } if (nesr_fr) sim_queue_fn_sf_write (current_cpu, frvbf_h_fr_set, nesr_drn, value); else sim_queue_fn_si_write (current_cpu, frvbf_h_gr_set, nesr_drn, value); nesr_drn++; regno++; } break; /* Only consider the first matching register. */ } } /* loop over active neear registers. */ }
/* Handle TRA and TIRA insns. */ void frv_itrap (SIM_CPU *current_cpu, PCADDR pc, USI base, SI offset) { SIM_DESC sd = CPU_STATE (current_cpu); host_callback *cb = STATE_CALLBACK (sd); USI num = ((base + offset) & 0x7f) + 0x80; #ifdef SIM_HAVE_BREAKPOINTS /* Check for breakpoints "owned" by the simulator first, regardless of --environment. */ if (num == TRAP_BREAKPOINT) { /* First try sim-break.c. If it's a breakpoint the simulator "owns" it doesn't return. Otherwise it returns and let's us try. */ sim_handle_breakpoint (sd, current_cpu, pc); /* Fall through. */ } #endif if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT) { frv_queue_software_interrupt (current_cpu, num); return; } switch (num) { case TRAP_SYSCALL : { CB_SYSCALL s; CB_SYSCALL_INIT (&s); s.func = GET_H_GR (7); s.arg1 = GET_H_GR (8); s.arg2 = GET_H_GR (9); s.arg3 = GET_H_GR (10); if (s.func == TARGET_SYS_exit) { sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1); } s.p1 = (PTR) sd; s.p2 = (PTR) current_cpu; s.read_mem = syscall_read_mem; s.write_mem = syscall_write_mem; cb_syscall (cb, &s); SET_H_GR (8, s.result); SET_H_GR (9, s.result2); SET_H_GR (10, s.errcode); break; } case TRAP_BREAKPOINT: sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); break; /* Add support for dumping registers, either at fixed traps, or all unknown traps if configured with --enable-sim-trapdump. */ default: #if !TRAPDUMP frv_queue_software_interrupt (current_cpu, num); return; #endif #ifdef TRAP_REGDUMP1 case TRAP_REGDUMP1: #endif #ifdef TRAP_REGDUMP2 case TRAP_REGDUMP2: #endif #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2)) { char buf[256]; int i, j; buf[0] = 0; if (STATE_TEXT_SECTION (sd) && pc >= STATE_TEXT_START (sd) && pc < STATE_TEXT_END (sd)) { const char *pc_filename = (const char *)0; const char *pc_function = (const char *)0; unsigned int pc_linenum = 0; if (bfd_find_nearest_line (STATE_PROG_BFD (sd), STATE_TEXT_SECTION (sd), (struct bfd_symbol **) 0, pc - STATE_TEXT_START (sd), &pc_filename, &pc_function, &pc_linenum) && (pc_function || pc_filename)) { char *p = buf+2; buf[0] = ' '; buf[1] = '('; if (pc_function) { strcpy (p, pc_function); p += strlen (p); } else { char *q = (char *) strrchr (pc_filename, '/'); strcpy (p, (q) ? q+1 : pc_filename); p += strlen (p); } if (pc_linenum) { sprintf (p, " line %d", pc_linenum); p += strlen (p); } p[0] = ')'; p[1] = '\0'; if ((p+1) - buf > sizeof (buf)) abort (); } } sim_io_printf (sd, "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n", (unsigned)pc, buf, (unsigned)base, (int)offset); for (i = 0; i < 64; i += 8) { long g0 = (long)GET_H_GR (i); long g1 = (long)GET_H_GR (i+1); long g2 = (long)GET_H_GR (i+2); long g3 = (long)GET_H_GR (i+3); long g4 = (long)GET_H_GR (i+4); long g5 = (long)GET_H_GR (i+5); long g6 = (long)GET_H_GR (i+6); long g7 = (long)GET_H_GR (i+7); if ((g0 | g1 | g2 | g3 | g4 | g5 | g6 | g7) != 0) sim_io_printf (sd, "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", i, i+7, g0, g1, g2, g3, g4, g5, g6, g7); } for (i = 0; i < 64; i += 8) { long f0 = (long)GET_H_FR (i); long f1 = (long)GET_H_FR (i+1); long f2 = (long)GET_H_FR (i+2); long f3 = (long)GET_H_FR (i+3); long f4 = (long)GET_H_FR (i+4); long f5 = (long)GET_H_FR (i+5); long f6 = (long)GET_H_FR (i+6); long f7 = (long)GET_H_FR (i+7); if ((f0 | f1 | f2 | f3 | f4 | f5 | f6 | f7) != 0) sim_io_printf (sd, "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", i, i+7, f0, f1, f2, f3, f4, f5, f6, f7); } sim_io_printf (sd, "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n", (long)GET_H_SPR (272), (long)GET_H_SPR (273), (long)GET_H_SPR (256), (long)GET_H_SPR (263)); } break; #endif } }