示例#1
0
/**
 * Reset TX & RX queue & statistics
 * \param pGmacd Pointer to GMAC Driver instance.
 */
void GMACD_Reset(sGmacd *pGmacd)
{
    Gmac *pHw = pGmacd->pHw;

    GMACD_ResetRx(pGmacd);
    GMACD_ResetTx(pGmacd);
    //memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats));
    GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN
                             | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT);
}
示例#2
0
/**
 * \brief Initialize the GMAC with the Gmac controller address
 *  \param pGmacd Pointer to GMAC Driver instance. 
 *  \param pHw    Pointer to HW address for registers.
 *  \param bID     HW ID for power management
 *  \param enableCAF    Enable/Disable CopyAllFrame.
 *  \param enableNBC    Enable/Disable NoBroadCast.
 */
 void GMACD_Init(sGmacd *pGmacd,
                Gmac *pHw,
                uint8_t bID, 
                uint8_t enableCAF, 
                uint8_t enableNBC )
{
    uint32_t dwNcfgr, dwDcfgr;
    
    /* Check parameters */
//    assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX);

    TRACE_DEBUG("GMAC_Init\n\r");

    /* Initialize struct */
    pGmacd->pHw = pHw;
    pGmacd->bId = bID;

    /* Power ON */
    PMC_EnablePeripheral(bID);

    /* Disable TX & RX and more */
    GMAC_NetworkControl(pHw, 0);
    GMAC_DisableAllQueueIt(pHw, ~0u);
    
    GMAC_ClearStatistics(pHw);
    /* Clear all status bits in the receive status register. */
    GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA |GMAC_RSR_HNO);

    /* Clear all status bits in the transmit status register */
    GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
                            | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
                            | GMAC_TSR_UND | GMAC_TSR_HRESP );

    /* Clear All interrupts */
    GMAC_GetItStatus(pHw, GMAC_QUE_0);
    GMAC_GetItStatus(pHw, GMAC_QUE_1);
    GMAC_GetItStatus(pHw, GMAC_QUE_2);

    /* Enable the copy of data into the buffers
       ignore broadcasts, and don't copy FCS. */
    dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64;
    /* enable 1536 buffer */
//    dwNcfgr |= GMAC_NCFGR_MAXFS;
    if( enableCAF ) {
        dwNcfgr |= GMAC_NCFGR_CAF;
    }
    if( enableNBC ) {
        dwNcfgr |= GMAC_NCFGR_NBC;
    }
    
    dwDcfgr = (GMAC_DCFGR_DRBS(8) |  (0<<8) | (0<<10) );
    GMAC_Configure(pHw, dwNcfgr);
    GMAC_DmaConfigure(pHw, dwDcfgr);
}
示例#3
0
文件: gmac.c 项目: djyos/djyos
static void __MacInitialize(tagMacDriver *pDrive)
{
    Gmac      *pHw;
    tagQueue  *que;
    u32        index;
    u32        value;

    pHw = pDrive->pHw;
    GMAC_DEBUG("Mac Initialize start...\n\r");
    //make it power on
    PMC_EnablePeripheral(pDrive->bId);
    //first,we must stop the device to receive or send
    GMAC_NetworkControl(pHw, 0);
    //disable all the interrupts
    GMAC_DisableAllQueueIt(pHw, ~0u);
    //do the stat clearing
    GMAC_ClearStatistics(pHw);
    /* Clear all status bits in the receive status register. */
    GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC
                    | GMAC_RSR_BNA |GMAC_RSR_HNO);
    /* Clear all status bits in the transmit status register */
    GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE
                            | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP
                            | GMAC_TSR_HRESP );

    //here we begin to configure the mac device
    for(index =0;index < CN_QUE_NUM;index ++)
    {
        que = &pDrive->queueList[CN_QUE_0];
        GMAC_GetItStatus(pHw, index);   //read for clear
        /*initialize the bd*/
        __MacBdSndInit(index);
        __MacBdRcvInit(index);
        /*set the dma configuration*/
        if(index == CN_QUE_0)
        {
            value = (GMAC_DCFGR_DRBS(que->rcvbuflen >> 6) )
                | GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS |GMAC_DCFGR_DDRP|GMAC_DCFGR_FBLDO_INCR4;
        }
        else
        {