void digitalWrite(int pin,digitalWriteState state)
{
if(pin < 100) return; //(~99:reserved)
if(pin < 200) //maryPinAssign(100~119?)
{
pin = pin - 100;
if(state == HIGH) //HIGH
{
if(LPC_GPIO_PORT->DIR0 & (1 << xpresso_pinAssign[pin * 2 + 1]))//pin is output
{
GPIOSetBitValue( xpresso_pinAssign[pin * 2], xpresso_pinAssign[pin * 2 + 1], 1);
}else //pin is input
{
//SetIOCON(xpresso_pinAssign[pin * 2], xpresso_pinAssign[pin * 2 + 1], IOCON_MODE_MASK, IOCON_MODE_PULLUP);
}
}else //LOW
{
if(LPC_GPIO_PORT->DIR0 & (1 << xpresso_pinAssign[pin * 2 + 1]))//pin is output
{
GPIOSetBitValue( xpresso_pinAssign[pin * 2], xpresso_pinAssign[pin * 2 + 1], 0);
}else // pin is input
{
//SetIOCON(xpresso_pinAssign[pin * 2], xpresso_pinAssign[pin * 2 + 1], IOCON_MODE_MASK, IOCON_MODE_INACTIVE);
}
}
}
return;
}
void chb_set_hgm(U8 enb)
{
if (enb)
{
GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 1);
}
else
{
GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 0);
}
}
/*****************************************************************************
** Function name: LoopbackTest
**
** Descriptions: Loopback test
**
** parameters: port #
** Returned value: None
**
*****************************************************************************/
void SSP_LoopbackTest( uint8_t portNum )
{
uint32_t i;
if ( portNum == 0 )
{
#if !USE_CS
/* Set SSEL pin to output low. */
GPIOSetBitValue( PORT0, 2, 0 );
#endif
i = 0;
while ( i <= SSP_BUFSIZE )
{
/* to check the RXIM and TXIM interrupt, I send a block data at one time
based on the FIFOSIZE(8). */
SSP_Send( portNum, (uint8_t *)&src_addr[i], FIFOSIZE );
/* If RX interrupt is enabled, below receive routine can be
also handled inside the ISR. */
SSP_Receive( portNum, (uint8_t *)&dest_addr[i], FIFOSIZE );
i += FIFOSIZE;
}
#if !USE_CS
/* Set SSEL pin to output high. */
GPIOSetBitValue( PORT0, 2, 1 );
#endif
}
else
{
#if !USE_CS
/* Set SSEL pin to output low. */
GPIOSetBitValue( PORT1, 23, 0 );
#endif
i = 0;
while ( i <= SSP_BUFSIZE )
{
/* to check the RXIM and TXIM interrupt, I send a block data at one time
based on the FIFOSIZE(8). */
SSP_Send( portNum, (uint8_t *)&src_addr[i], FIFOSIZE );
/* If RX interrupt is enabled, below receive routine can be
also handled inside the ISR. */
SSP_Receive( portNum, (uint8_t *)&dest_addr[i], FIFOSIZE );
i += FIFOSIZE;
}
#if !USE_CS
/* Set SSEL pin to output high. */
GPIOSetBitValue( PORT1, 23, 1 );
#endif
}
return;
}
int main (void)
{
SystemCoreClockUpdate();
/* TEST_TIMER_NUM is either 0 or 1 for 32-bit timer 0 or 1. */
init_timer32(TEST_TIMER_NUM, TIME_INTERVAL);
enable_timer32(TEST_TIMER_NUM);
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
/* Set port 0_7 to output */
GPIOSetDir( 0, 7, 1 );
while (1) /* Loop forever */
{
#if TEST_TIMER_NUM
/* I/O configuration and LED setting pending. */
if ( (timer32_1_counter[0] > 0) && (timer32_1_counter[0] <= 50) )
{
GPIOSetBitValue( 0, 7, 0 );
}
if ( (timer32_1_counter[0] > 50) && (timer32_1_counter[0] <= 100) )
{
GPIOSetBitValue( 0, 7, 1 );
}
else if ( timer32_1_counter[0] > 100 )
{
timer32_1_counter[0] = 0;
}
#else
/* I/O configuration and LED setting pending. */
if ( (timer32_0_counter[0] > 0) && (timer32_0_counter[0] <= 50) )
{
GPIOSetBitValue( 0, 7, 0 );
}
if ( (timer32_0_counter[0] > 50) && (timer32_0_counter[0] <= 100) )
{
GPIOSetBitValue( 0, 7, 1 );
}
else if ( timer32_0_counter[0] > 100 )
{
timer32_0_counter[0] = 0;
}
#endif
}
}
int main(void) {
SystemCoreClockUpdate();
GPIOInit();
GPIOSetDir(PORT_TEST, PIN_TEST, 1); // 1 means output
GPIOSetBitValue(PORT_TEST, PIN_TEST, 0);
for(;;);
}
/*****************************************************************************
** Function name: BOD_IRQHandler
**
** Descriptions: BOD interrupt handler
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void BOD_IRQHandler(void)
{
if ( LPC_SYSCON->SYSRSTSTAT & BOD_RESET )
{
/* If the BOD RESET has occured, disable the BOD interrupt,
or we will stuck here serving BOD interrupt instead of
LED blinking showing BOD RESET. */
NVIC_DisableIRQ(BOD_IRQn);
return;
}
bod_counter++;
/* Turn on BOD RST LED only, turn off the rest. */
GPIOSetBitValue( 0, BOD_INTERRUPT_LED, 1 );
GPIOSetBitValue( 0, BOD_RESET_LED, 0 );
GPIOSetBitValue( 0, POR_RESET_LED, 0 );
return;
}
int main (void)
{
SystemCoreClockUpdate();
/* Initialize 32-bits timer 0 */
init_timer32(0, TIME_INTERVAL);
enable_timer32(0);
/* Initialize the PWM in timer32_1 enabling match0 output */
init_timer32PWM(1, period, MATCH0);
setMatch_timer32PWM (1, 0, period/4);
enable_timer32(1);
/* Initialize the PWM in timer16_0 enabling match1 output */
init_timer16PWM(0, period, MATCH1, 0);
setMatch_timer16PWM (0, 1, period/2);
enable_timer16(0);
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
/* Set port 1_19 to output */
GPIOSetDir( 1, 6, 1 );
while (1) /* Loop forever */
{
/* I/O configuration and LED setting pending. */
if ( (timer32_0_counter[0] > 0) && (timer32_0_counter[0] <= 50) )
{
GPIOSetBitValue( 1, 6, 0 );
}
if ( (timer32_0_counter[0] > 50) && (timer32_0_counter[0] <= 100) )
{
GPIOSetBitValue( 1, 6, 1 );
}
else if ( timer32_0_counter[0] > 100 )
{
timer32_0_counter[0] = 0;
}
}
}
err_t msgSend(uint16_t targetAddr, msg_MessageType_t msgType, uint8_t *payload, uint8_t payloadLength)
{
uint8_t msgLength = payloadLength + 9;
uint8_t results;
uint32_t timestamp;
/* Make sure payload is within limits */
/* ToDo: Throw proper error code/msg */
if (msgLength > CHB_MAX_PAYLOAD)
return ERROR_CHIBI_PAYLOADOVERFLOW;
/* Clear message buffer */
memset(&_msg, 0x00, CHB_MAX_PAYLOAD);
/* Message Envelope (9 bytes) + Payload
==========================================================================
U16 Message ID Sequential message ID
U8 Message Type Sensor results, Alert, File, etc.
U32 Timestamp Current second tick count
U8 Reserved Reserved
U8 Payload Length Payload length in bytes
... Payload Message payload
------------------------------------------------------------------------*/
/* Sequential Message ID (U16) */
*(uint16_t*)&_msg = _msg_msgID++;
/* Message Type (U8) */
_msg[2] = msgType;
/* Timestamp (U32) */
/* Need to use memcpy here since the M0 can't do unaligned accesses! */
timestamp = delayGetSecondsActive();
memcpy(&_msg[3], ×tamp, 4);
/* Reserved (U8) */
_msg[7] = 0x00;
/* Payload Length (U8) */
_msg[8] = payloadLength;
/* Message Payload (91 bytes max) */
memcpy(&_msg[9], payload, payloadLength);
/*===================================================================== */
do
{
/* Send message via Chibi */
// chb_pcb_t *pcb = chb_get_pcb();
GPIOSetBitValue(CFG_LED_PORT, CFG_LED_PIN, CFG_LED_ON);
results = chb_write(targetAddr, _msg, msgLength);
GPIOSetBitValue(CFG_LED_PORT, CFG_LED_PIN, CFG_LED_OFF);
} while(0);
/* Return an appropriate error code depending on the write status */
switch(results)
{
case CHB_NO_ACK:
return ERROR_CHIBI_NOACK;
case CHB_CHANNEL_ACCESS_FAILURE:
return ERROR_CHIBI_CHANACCESSFAILURE;
default:
return ERROR_NONE;
}
}
static error_t chb_radio_init()
{
U8 ieee_addr[8];
// reset chip (this can fail if there is a HW or config problem)
error_t error = chb_reset();
if (error)
{
return error;
}
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
#if (CFG_CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
// set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm)
chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h
chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h
chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
#if (CHB_CC1190_PRESENT)
// set high gain mode pin to output and init to zero
GPIOSetDir(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 1);
GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 0);
// set external power amp on AT86RF212
chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS);
// set power to lowest level possible
chb_set_pwr(0xd); // set to -11 dBm
#endif
// set interrupt/gpio pin to input
GPIOSetDir(CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0);
// Channel 0, sense (0=edge, 1=level), polarity (0=low/falling, 1=high/rising)
GPIOSetPinInterrupt( 0, CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0, 1 );
// Enable interrupt
// GPIOPinIntEnable( 0, 0 );
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
printf(chb_err_init);
return ERROR_DEVICENOTINITIALISED;
}
return ERROR_NONE;
}
/*****************************************************************************
** Function name: SEEPROMTest
**
** Descriptions: Serial EEPROM(Atmel 25xxx) test
**
** parameters: port #
** Returned value: None
**
*****************************************************************************/
void SSP_SEEPROMTest( uint8_t portNum )
{
uint32_t i, timeout;
if ( portNum == 0 )
{
LPC_IOCON->PIO0_2 &= ~0x07; /* SSP SSEL is a GPIO pin */
GPIOSetBitValue( PORT0, 2, 1 );
/* port0, bit 2 is set to GPIO output and high */
GPIOSetDir( PORT0, 2, 1 );
GPIOSetBitValue( PORT0, 2, 0 );
/* Test Atmel AT25DF041 Serial flash. */
src_addr[0] = WREN; /* set write enable latch */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
for ( i = 0; i < 0x80; i++ ); /* delay minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = RDSR; /* check status to see if write enabled is latched */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
SSP_Receive( portNum, (uint8_t *)dest_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
if ( (dest_addr[0] & (RDSR_WEN|RDSR_RDY)) != RDSR_WEN )
/* bit 0 to 0 is ready, bit 1 to 1 is write enable */
{
while ( 1 );
}
for ( i = 0; i < 0x80; i++ ); /* delay minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = WRSR;
src_addr[1] = 0x00; /* Make the whole device unprotected. */
SSP_Send( portNum, (uint8_t *)src_addr, 2 );
GPIOSetBitValue( PORT0, 2, 1 );
for ( i = 0; i < 0x80; i++ ); /* delay minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = RDSR; /* check status to see if write enabled is latched */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
SSP_Receive( portNum, (uint8_t *)dest_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
if ( (dest_addr[0] & (RDSR_WEN|RDSR_RDY)) != RDSR_WEN )
/* bit 0 to 0 is ready, bit 1 to 1 is write enable */
{
while ( 1 );
}
for ( i = 0; i < 0x80; i++ ); /* delay minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = CHIP_ERASE; /* Write command is 0x02, low 256 bytes only */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
for ( i = 0; i < 0x1400000; i++ ); /* Be careful with the dumb delay, it
may vary depending on the system clock. */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = RDSR; /* check status to see if write enabled is latched */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
SSP_Receive( portNum, (uint8_t *)dest_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
if ( (dest_addr[0] & (RDSR_EPE|RDSR_RDY)) != 0x0 )
/* bit 0 to 0 is ready, bit 1 to 1 is write enable */
{
while ( 1 );
}
GPIOSetBitValue( PORT0, 2, 0 );
/* Test Atmel AT25DF041 Serial flash. */
src_addr[0] = WREN; /* set write enable latch */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
for ( i = 0; i < 0x80; i++ ); /* delay minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = RDSR; /* check status to see if write enabled is latched */
SSP_Send( portNum, (uint8_t *)src_addr, 1 );
SSP_Receive( portNum, (uint8_t *)dest_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
if ( (dest_addr[0] & (RDSR_WEN|RDSR_RDY)) != RDSR_WEN )
/* bit 0 to 0 is ready, bit 1 to 1 is write enable */
{
while ( 1 );
}
for ( i = 0; i < SSP_BUFSIZE; i++ ) /* Init RD and WR buffer */
{
src_addr[i+SFLASH_INDEX] = i; /* leave four bytes for cmd and offset(16 bits) */
dest_addr[i] = 0;
}
/* please note the first four bytes of WR and RD buffer is used for
commands and offset, so only 4 through SSP_BUFSIZE is used for data read,
write, and comparison. */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = WRITE; /* Write command is 0x02, low 256 bytes only */
src_addr[1] = 0x00; /* write address offset MSB is 0x00 */
src_addr[2] = 0x00; /* write address offset LSB is 0x00 */
src_addr[3] = 0x00; /* write address offset LSB is 0x00 */
SSP_Send( portNum, (uint8_t *)src_addr, SSP_BUFSIZE );
GPIOSetBitValue( PORT0, 2, 1 );
for ( i = 0; i < 0x400000; i++ ); /* Be careful with the dumb delay, it
may vary depending on the system clock. */
timeout = 0;
while ( timeout < MAX_TIMEOUT )
{
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = RDSR; /* check status to see if write cycle is done or not */
SSP_Send( portNum, (uint8_t *)src_addr, 1);
SSP_Receive( portNum, (uint8_t *)dest_addr, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
if ( (dest_addr[0] & RDSR_RDY) == 0x00 ) /* bit 0 to 0 is ready */
{
break;
}
timeout++;
}
if ( timeout == MAX_TIMEOUT )
{
while ( 1 );
}
for ( i = 0; i < 0x80; i++ ); /* delay, minimum 250ns */
GPIOSetBitValue( PORT0, 2, 0 );
src_addr[0] = READ; /* Read command is 0x03, low 256 bytes only */
src_addr[1] = 0x00; /* Read address offset MSB is 0x00 */
src_addr[2] = 0x00; /* Read address offset LSB is 0x00 */
src_addr[3] = 0x00; /* Read address offset LSB is 0x00 */
SSP_Send( portNum, (uint8_t *)src_addr, SFLASH_INDEX );
SSP_Receive( portNum, (uint8_t *)&dest_addr[SFLASH_INDEX], SSP_BUFSIZE-SFLASH_INDEX );
GPIOSetBitValue( PORT0, 2, 1 );
}
else /* Port 1 */
{
/* Test on Port 0 only. */
while ( 1 );
}
return;
}
void ui_task( void * data)
{
int i;
portBASE_TYPE res;
int count = 10;
char acTempStr[20];
uint8_t acTemp[2];
uint8_t bMosfetEnabled = 0;
// init LCD;
lcd_clear_all();
lcd_init();
lcd_led_power(1);
//lcd_test(0);
lcd_text(32,10,3,"NFC",0);
lcd_text(12,40,1,"ipTronix Arrow NXP",0);
lcd_update(0,63);
lcd_clear_all();
vTaskDelay(1500);
lcd_clear_all();
for (;;)
{
KEY_EVENT_t key;
char str[30];
lcd_text(12,10,1,"Please approach card",0);
lcd_update(0,63);
do
{
res = xQueueReceive(xUIQueue,&taginfo,/*portMAX_DELAY*/20);
key=CAP_KEY_GetEvent();
count++;
if ((count >= 3) && (res!= pdPASS))
{
count = 0;
I2CRead(0x90,0,&acTemp[0],2);
sprintf(acTempStr,"Temperature %d",acTemp[0]);
lcd_text(12,27,1,acTempStr,0);
sprintf(acTempStr,"Keys %d",keystate);
lcd_text(28,46,2,acTempStr,0);
lcd_update(0,63);
}
if (bMosfetEnabled)
{
bMosfetEnabled = 0;
GPIOSetBitValue(PIN_MOSFET,0);
}
else
{
bMosfetEnabled = 1;
GPIOSetBitValue(PIN_MOSFET,1);
}
if (GPIOGetPinValue( PIN_ISP ) == 0)
{
lcd_clear_all();
lcd_text(52,26,2,"ISP",0);
lcd_update(0,63);
NVIC_SystemReset();
}
if (GPIOGetPinValue( PIN_CAL_DET ))
{
NVIC_SystemReset();
}
} while (res!= pdPASS) ;
if (res == pdPASS)
{
lcd_clear_all();
sprintf(str, "UID ");
for (i=0;i<taginfo.szUidLen;i++)
{
sprintf(&str[4+i*2],"%02X",taginfo.abtUid[i]);
}
lcd_text(0,0,1,str,0);
sprintf(str,"NDEF Len %d",taginfo.msgLen);
lcd_text(0,12,1,str,0);
snprintf(str,30,"MSG %s",taginfo.msg);
lcd_text(0,24,1,str,0);
lcd_update(0,63);
vTaskDelay(1500);
lcd_clear_all();
count = 10;
}
lcd_update(0,63);
}
}
/*****************************************************************************
** Function name: SSP_IOConfig
**
** Descriptions: SSP port initialization routine
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void SSP_IOConfig( uint8_t portNum )
{
if ( portNum == 0 )
{
LPC_SYSCON->PRESETCTRL |= (0x1<<0);
LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<11);
LPC_SYSCON->SSP0CLKDIV = 0x02; /* Divided by 2 */
LPC_IOCON->PIO0_8 &= ~0x07; /* SSP I/O config */
LPC_IOCON->PIO0_8 |= 0x01; /* SSP MISO */
LPC_IOCON->PIO0_9 &= ~0x07;
LPC_IOCON->PIO0_9 |= 0x01; /* SSP MOSI */
#ifdef __JTAG_DISABLED
LPC_IOCON->SWCLK_PIO0_10 &= ~0x07;
LPC_IOCON->SWCLK_PIO0_10 |= 0x02; /* SSP CLK */
#else
#if 1
LPC_IOCON->PIO1_29 = 0x01; /* SSP CLK */
#else
LPC_IOCON->PIO0_6 = 0x02; /* SSP CLK */
#endif
#endif /* endif __JTAG_DISABLED */
#if USE_CS
LPC_IOCON->PIO0_2 &= ~0x07;
LPC_IOCON->PIO0_2 |= 0x01; /* SSP SSEL */
#else
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
LPC_IOCON->PIO0_2 &= ~0x07; /* SSP SSEL is a GPIO pin */
/* port0, bit 2 is set to GPIO output and high */
GPIOSetDir( PORT0, 2, 1 );
GPIOSetBitValue( PORT0, 2, 1 );
#endif
}
else /* port number 1 */
{
LPC_SYSCON->PRESETCTRL |= (0x1<<2);
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<18);
LPC_SYSCON->SSP1CLKDIV = 0x02; /* Divided by 2 */
LPC_IOCON->PIO1_21 &= ~0x07; /* SSP I/O config */
LPC_IOCON->PIO1_21 |= 0x02; /* SSP MISO */
LPC_IOCON->PIO1_22 &= ~0x07;
LPC_IOCON->PIO1_22 |= 0x02; /* SSP MOSI */
LPC_IOCON->PIO1_20 &= ~0x07;
LPC_IOCON->PIO1_20 |= 0x02; /* SSP CLK */
#if USE_CS
LPC_IOCON->PIO1_23 &= ~0x07;
LPC_IOCON->PIO1_23 |= 0x02; /* SSP SSEL */
#else
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6);
LPC_IOCON->PIO1_23 &= ~0x07; /* SSP SSEL is a GPIO pin */
/* port1, bit 19 is set to GPIO output and high */
GPIOSetDir( PORT1, 23, 1 );
GPIOSetBitValue( PORT1, 23, 1 );
#endif
}
return;
}
void ui_task( void * data)
{
portBASE_TYPE res;
m_eMode = mdAUTHENTICATE;
// init LCD;
lcd_clear_all();
lcd_init();
lcd_led_power(1);
//lcd_test(0);
lcd_text(32,10,3,"NFC",0);
lcd_text(12,40,1,"ipTronix Arrow NXP",0);
lcd_update(0,63);
lcd_clear_all();
vTaskDelay(1500);
for (;;)
{
char str[30];
lcd_clear_all();
lcd_text(32,0,1,"Authentication",0);
lcd_text(32,20,2,"Scan card",0);
switch (m_eMode)
{
case mdAUTHENTICATE:
lcd_text(10,40,2,"AUTHENTICATE",1);
break;
case mdAUTHORIZE:
lcd_text(22,40,2,"AUTHORIZE",1);
break;
case mdDENY:
lcd_text(42,40,2,"DENY",1);
break;
}
lcd_update(0,63);
do
{
key=CAP_KEY_GetEvent();
res = xQueueReceive(xUIQueue,&payload,100);
if (GPIOGetPinValue( PIN_ISP ) == 0)
{
lcd_clear_all();
lcd_text(52,26,2,"ISP",0);
lcd_update(0,63);
NVIC_SystemReset();
}
} while ((key==keNONE) && (res!= pdPASS));
if (key==keK3_PRESS || key==keK3_REPEAT)
{
if (m_eMode<mdDENY)
m_eMode++;
else
m_eMode=mdAUTHENTICATE;
}
else if (key==keK1_PRESS || key==keK1_REPEAT)
{
if (m_eMode>mdAUTHENTICATE)
m_eMode--;
else
m_eMode = mdDENY;
}
key=keNONE;
if (res==pdPASS)
{
lcd_clear_all();
snprintf(str, sizeof(payload.name),"Name %s", payload.name);
lcd_text(0,20,2,str,0);
sprintf(str,"Access %08X",payload.access_rights);
lcd_text(0,40,2,str,0);
lcd_update(0,63);
if (payload.access_rights==0xffffffff)
GPIOSetBitValue(PIN_MOSFET,1);
vTaskDelay(1500);
GPIOSetBitValue(PIN_MOSFET,0);
}
}
}
