int init_spi(void)
{
#if CFG_CC3000_SPI_PORT == 1
ssp1Init();
#else
ssp0Init();
#endif
/* Set VBAT EN pin to output */
LPC_GPIO->DIR[CFG_CC3000_EN_PORT] |= (1 << CFG_CC3000_EN_PIN);
LPC_GPIO->SET[CFG_CC3000_EN_PORT] = (1 << CFG_CC3000_EN_PIN);
delay(100);
/* Set CS pin to output */
LPC_GPIO->DIR[CFG_CC3000_CS_PORT] |= (1 << CFG_CC3000_CS_PIN);
CC3000_DEASSERT_CS;
/* Set interrupt/gpio pin to input */
LPC_GPIO->DIR[CFG_CC3000_IRQ_PORT] &= ~(1 << CFG_CC3000_IRQ_PIN);
/* Channel 2, sense (0=edge, 1=level), polarity (0=low/falling, 1=high/rising) */
GPIOSetPinInterrupt( 2, CFG_CC3000_IRQ_PORT, CFG_CC3000_IRQ_PIN, 0, 1 );
/* Enable interrupt 2 on falling edge */
GPIOPinIntEnable( 2, 0 );
return(ESUCCESS);
}
static error_t chb_radio_init()
{
U8 ieee_addr[8];
// reset chip (this can fail if there is a HW or config problem)
error_t error = chb_reset();
if (error)
{
return error;
}
// disable intps while we config the radio
chb_reg_write(IRQ_MASK, 0);
// force transceiver off while we configure the intps
chb_reg_read_mod_write(TRX_STATE, CMD_FORCE_TRX_OFF, 0x1F);
// make sure the transceiver is in the off state before proceeding
while ((chb_reg_read(TRX_STATUS) & 0x1f) != TRX_OFF);
// set radio cfg parameters
// **note** uncomment if these will be set to something other than default
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_FRAME_RETRIES << CHB_MAX_FRAME_RETRIES_POS, 0xF << CHB_MAX_FRAME_RETRIES_POS);
//chb_reg_read_mod_write(XAH_CTRL_0, CHB_MAX_CSMA_RETRIES << CHB_MAX_CSMA_RETIRES_POS, 0x7 << CHB_MAX_CSMA_RETIRES_POS);
//chb_reg_read_mod_write(CSMA_SEED_1, CHB_CSMA_SEED1 << CHB_CSMA_SEED1_POS, 0x7 << CHB_CSMA_SEED1_POS);
//chb_ret_write(CSMA_SEED0, CHB_CSMA_SEED0);
//chb_reg_read_mod_write(PHY_CC_CCA, CHB_CCA_MODE << CHB_CCA_MODE_POS,0x3 << CHB_CCA_MODE_POS);
//chb_reg_write(CCA_THRES, CHB_CCA_ED_THRES);
// set frame version that we'll accept
chb_reg_read_mod_write(CSMA_SEED_1, CHB_FRM_VER << CHB_FVN_POS, 3 << CHB_FVN_POS);
// set interrupt mask
// re-enable intps while we config the radio
chb_reg_write(IRQ_MASK, (1<<IRQ_RX_START) | (1<<IRQ_TRX_END));
#if (CFG_CHIBI_PROMISCUOUS == 0)
// set autocrc mode
chb_reg_read_mod_write(TRX_CTRL_1, 1 << CHB_AUTO_CRC_POS, 1 << CHB_AUTO_CRC_POS);
#endif
// set up default phy modulation, data rate and power (Ex. OQPSK, 100 kbps, 868 MHz, 3dBm)
chb_set_mode(CFG_CHIBI_MODE); // Defined in projectconfig.h
chb_set_pwr(CFG_CHIBI_POWER); // Defined in projectconfig.h
chb_set_channel(CFG_CHIBI_CHANNEL); // Defined in projectconfig.h
// set fsm state
// put trx in rx auto ack mode
chb_set_state(RX_STATE);
// set pan ID
chb_reg_write16(PAN_ID_0, CFG_CHIBI_PANID); // Defined in projectconfig.h
// set short addr
// NOTE: Possibly get this from EEPROM
chb_reg_write16(SHORT_ADDR_0, chb_get_short_addr());
// set long addr
// NOTE: Possibly get this from EEPROM
chb_get_ieee_addr(ieee_addr);
chb_reg_write64(IEEE_ADDR_0, ieee_addr);
#if (CHB_CC1190_PRESENT)
// set high gain mode pin to output and init to zero
GPIOSetDir(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 1);
GPIOSetBitValue(CFG_CHIBI_CC1190_HGM_PORT, CFG_CHIBI_CC1190_HGM_PIN, 0);
// set external power amp on AT86RF212
chb_reg_read_mod_write(TRX_CTRL_1, 1<<CHB_PA_EXT_EN_POS, 1<<CHB_PA_EXT_EN_POS);
// set power to lowest level possible
chb_set_pwr(0xd); // set to -11 dBm
#endif
// set interrupt/gpio pin to input
GPIOSetDir(CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0);
// Channel 0, sense (0=edge, 1=level), polarity (0=low/falling, 1=high/rising)
GPIOSetPinInterrupt( 0, CFG_CHIBI_EINTPORT, CFG_CHIBI_EINTPIN, 0, 1 );
// Enable interrupt
// GPIOPinIntEnable( 0, 0 );
if (chb_get_state() != RX_STATE)
{
// ERROR occurred initializing the radio. Print out error message.
printf(chb_err_init);
return ERROR_DEVICENOTINITIALISED;
}
return ERROR_NONE;
}