void Open_ACMP(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD.9 multi-function pin for ACMP1 positive input pin */ SYS->GPD_MFPH &= ~SYS_GPD_MFPH_PD9MFP_Msk; SYS->GPD_MFPH |= SYS_GPD_MFPH_PD9MFP_ACMP1_P3; /* Set PD.0 multi-function pin for ACMP1 negative input pin */ SYS->GPD_MFPL &= ~SYS_GPD_MFPL_PD0MFP_Msk; SYS->GPD_MFPL |= SYS_GPD_MFPL_PD0MFP_ACMP1_N; /* Disable digital input path of analog pin ACMP1_P3 and ACMP1_N to prevent leakage */ GPIO_DISABLE_DIGITAL_PATH(PD, (1ul << 9)); GPIO_DISABLE_DIGITAL_PATH(PD, (1ul << 0)); /* Enable ACMP01 peripheral clock */ CLK_EnableModuleClock(ACMP01_MODULE); /* Configure ACMP1. Enable ACMP1 and select ACMP1_N as negative input. */ ACMP_Open(ACMP01, 1, ACMP_CTL_NEGSEL_PIN, ACMP_CTL_HYSTERESIS_DISABLE); /* select ACMP1_p3 as positive input pin */ ACMP_SELECT_P(ACMP01, 1, ACMP_CTL_POSSEL_P3); }
//============================================================================= __myevic__ void InitEADC() { if ( ISCUBO200 || ISRX200S || ISRX23 || ISRX300 ) { // Configure PB.0 - PB.7 analog input pins SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk | SYS_GPB_MFPL_PB7MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3 | SYS_GPB_MFPL_PB4MFP_EADC_CH4 | SYS_GPB_MFPL_PB5MFP_EADC_CH13 | SYS_GPB_MFPL_PB6MFP_EADC_CH14 | SYS_GPB_MFPL_PB7MFP_EADC_CH15); // Disable PB.0 - PB.7 digital input paths to avoid leakage currents GPIO_DISABLE_DIGITAL_PATH( PB, 0xFF ); } else if ( ISEGRIPII || ISEVICAIO ) { // Configure PB.0,1,2,6 analog input pins SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk ); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB6MFP_EADC_CH14 ); // Disable PB.0,1,2,6 digital input paths to avoid leakage currents GPIO_DISABLE_DIGITAL_PATH( PB, 0x47 ); } else { // Configure PB.0 - PB.6 analog input pins SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk ); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3 | SYS_GPB_MFPL_PB4MFP_EADC_CH4 | SYS_GPB_MFPL_PB5MFP_EADC_CH13 | SYS_GPB_MFPL_PB6MFP_EADC_CH14); // Disable PB.0 - PB.6 digital input paths to avoid leakage currents GPIO_DISABLE_DIGITAL_PATH( PB, 0x7F ); } }
// --------------------------------------------------------------------------------------- // Gas ADC initialize setting // Set PB2 as ADC converter // Select APB0/8 as ADC module clock source // --------------------------------------------------------------------------------------- void ID_Init() { SYS_UnlockReg(); /* Enable EADC module clock */ CLK_EnableModuleClock(EADC_MODULE); /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */ CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); SYS_LockReg(); /* Configure the GPB0 - GPB3 ADC analog input pins. */ SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk; SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_EADC_CH0; GPIO_DISABLE_DIGITAL_PATH(PB, BIT0); /* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */ EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END); EADC_SetInternalSampleTime(EADC, 6); /* Configure the sample module 0 for analog input channel 1 and software trigger source.*/ EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 0); /* Clear the A/D ADINT0 interrupt flag for safe */ EADC_CLR_INT_FLAG(EADC, 0x1); /* Enable the sample module 0 interrupt. */ EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt. EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt. }
void ADC_Init() { uint8_t i; IRQn_Type irqNum[4] = {ADC00_IRQn, ADC01_IRQn, ADC02_IRQn, ADC03_IRQn}; // Enable VBAT unity gain buffer SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk; // Set internal 2.56V voltage reference SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V; // Configure PB.0 - PB.6 analog input pins SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3 | SYS_GPB_MFPL_PB4MFP_EADC_CH4 | SYS_GPB_MFPL_PB5MFP_EADC_CH13 | SYS_GPB_MFPL_PB6MFP_EADC_CH14); // Disable PB.0 - PB.6 digital input paths to avoid leakage currents GPIO_DISABLE_DIGITAL_PATH(PB, 0x7F); // Configure ADC (single-ended) EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END); EADC_SetInternalSampleTime(EADC, 6); // Enable interrupts for(i = 0; i < 4; i++) { EADC_ENABLE_INT(EADC, 1 << i); NVIC_EnableIRQ(irqNum[i]); } }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Select HCLK clock source as HIRC and and HCLK source divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/ CLK_DisablePLL(); /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set core clock as PLL_CLOCK from PLL */ CLK_SetCoreClock(PLL_CLOCK); /* Enable UART module clock */ CLK_EnableModuleClock(UART0_MODULE); /* Select UART module clock source as HXT and UART module clock divider as 1 */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); /* Enable EADC module clock */ CLK_EnableModuleClock(EADC_MODULE); /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */ CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD multi-function pins for UART0 RXD and TXD */ SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk); SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD); /* Configure the GPB0 - GPB3 ADC analog input pins. */ SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3); /* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */ GPIO_DISABLE_DIGITAL_PATH(PB, 0xF); }
//============================================================================= __myevic__ void InitEADC() { // Configure PB.0 - PB.6 analog input pins SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk | SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk | SYS_GPB_MFPL_PB4MFP_Msk | SYS_GPB_MFPL_PB5MFP_Msk | SYS_GPB_MFPL_PB6MFP_Msk); SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 | SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3 | SYS_GPB_MFPL_PB4MFP_EADC_CH4 | SYS_GPB_MFPL_PB5MFP_EADC_CH13 | SYS_GPB_MFPL_PB6MFP_EADC_CH14); // Disable PB.0 - PB.6 digital input paths to avoid leakage currents GPIO_DISABLE_DIGITAL_PATH( PB, 0x7F ); }
/*---------------------------------------------------------------------------------------------------------*/ void SYS_Init(void) { /* Unlock protected registers */ SYS_UnlockReg(); /* Set HCLK source form HXT and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1)); /* Enable external 12MHz HXT, 32KHz LXT and HIRC */ CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk); /* Waiting for clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk); /* Set HCLK frequency 42MHz */ CLK_SetCoreClock(42000000); /* Enable IP clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(TMR0_MODULE); /* Enable DAC clock */ CLK->APBCLK |= CLK_APBCLK_DAC_EN_Msk; /* Enable DMA clock */ CLK->AHBCLK |= CLK_AHBCLK_DMA_EN_Msk; /* Select IP clock source */ CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_UART_CLK_DIVIDER(1)); /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PA multi-function pins for UART0 RXD and TXD */ SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk); SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX ); /* Set PC.6 multi-function pin for DAC channel 0 */ SYS->PC_L_MFP &= ~(SYS_PC_L_MFP_PC6_MFP_Msk); SYS->PC_L_MFP |= SYS_PC_L_MFP_PC6_MFP_DA_OUT0; /* Disable digital input path for both PC.6 */ GPIO_DISABLE_DIGITAL_PATH(PC, 1 << 6); /* Lock protected registers */ SYS_LockReg(); }
void Battery_Init(void) { #ifdef M451 SYS_UnlockReg(); /* Enable EADC module clock */ CLK_EnableModuleClock(EADC_MODULE); /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */ CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); SYS_LockReg(); /* Configure the GPB0 - GPB3 ADC analog input pins. */ SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB2MFP_Msk; SYS->GPB_MFPL |= SYS_GPB_MFPL_PB2MFP_EADC_CH2; GPIO_DISABLE_DIGITAL_PATH(PB, 0x4); /* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */ EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END); EADC_SetInternalSampleTime(EADC, 6); /* Configure the sample module 0 for analog input channel 2 and software trigger source.*/ EADC_ConfigSampleModule(EADC, 0, EADC_SOFTWARE_TRIGGER, 2); /* Clear the A/D ADINT0 interrupt flag for safe */ EADC_CLR_INT_FLAG(EADC, 0x1); /* Enable the sample module 0 interrupt. */ EADC_ENABLE_INT(EADC, 0x1);//Enable sample module A/D ADINT0 interrupt. EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 0, 0x1);//Enable sample module 0 interrupt. /* Reset the ADC interrupt indicator and trigger sample module 0 to start A/D conversion */ g_u32AdcIntFlag = 0; /* Enable battery detect circuit (PA3=1)*/ GPIO_SetMode(PA, BIT3, GPIO_MODE_OUTPUT); PA3=1; #else /* TBD.. */ #endif }
/* ---------------------------------------------------------------------------------------*/ void Battery_Init() { SYS_UnlockReg(); /* Enable EADC module clock */ CLK_EnableModuleClock(EADC_MODULE); /* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */ CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); SYS_LockReg(); /* Configure the GPB0 - GPB3 ADC analog input pins. */ SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB1MFP_Msk; SYS->GPB_MFPL |= SYS_GPB_MFPL_PB1MFP_EADC_CH1; GPIO_DISABLE_DIGITAL_PATH(PB, BIT1); //LED SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk); SYS->GPA_MFPL |= SYS_GPA_MFPL_PA2MFP_GPIO; GPIO_SetMode(PA,BIT2,GPIO_MODE_OUTPUT); PA2 = 1; /* Set the ADC internal sampling time, input mode as single-end and enable the A/D converter */ EADC_Open(EADC, EADC_CTL_DIFFEN_SINGLE_END); EADC_SetInternalSampleTime(EADC, 6); /* Configure the sample module 0 for analog input channel 1 and software trigger source.*/ EADC_ConfigSampleModule(EADC, 1, EADC_SOFTWARE_TRIGGER, 1); /* Clear the A/D ADINT0 interrupt flag for safe */ EADC_CLR_INT_FLAG(EADC, 0x2); /* Enable the sample module 0 interrupt. */ EADC_ENABLE_INT(EADC, 0x2);//Enable sample module A/D ADINT0 interrupt. EADC_ENABLE_SAMPLE_MODULE_INT(EADC, 1, 0x2);//Enable sample module 0 interrupt. BatDev.DevDesc.DevDesc_leng = 26; //Report descriptor BatDev.DevDesc.RptDesc_leng = 36; //Report descriptor BatDev.DevDesc.InRptLeng = 5; //Input report BatDev.DevDesc.OutRptLeng = 0; //Output report BatDev.DevDesc.GetFeatLeng = 6; //Get feature BatDev.DevDesc.SetFeatLeng = 6; //Set feature BatDev.DevDesc.CID = 0; //manufacturers ID BatDev.DevDesc.DID = 0; //Product ID BatDev.DevDesc.PID = 0; //Device firmware revision BatDev.DevDesc.UID = 0; //Device Class type BatDev.DevDesc.UCID = 0; //reserve /* Feature */ BatDev.Feature.data1.minimum = 0; //Sleep period BatDev.Feature.data1.maximum = 1024; BatDev.Feature.data1.value = 100; BatDev.Feature.data2.minimum = 0; //Battery alerm value BatDev.Feature.data2.maximum = 100; BatDev.Feature.data2.value = 50; BatDev.Feature.arg[0] = 1; BatDev.Feature.arg[1] = 2; BatDev.Feature.datalen[0] = 2; BatDev.Feature.datalen[1] = 2; BatDev.Feature.dataNum = 2; /* Input */ BatDev.Input.data1.minimum = 0; //Battery value BatDev.Input.data1.maximum = 100; BatDev.Input.data1.value = 100; BatDev.Input.data2.minimum = 0; //Over flag BatDev.Input.data2.maximum = 1; BatDev.Input.data2.value = 0; BatDev.Input.arg[0] = 1; BatDev.Input.arg[1] = 2; BatDev.Input.datalen[0] = 2; BatDev.Input.datalen[1] = 1; BatDev.Input.dataNum = 2; /* Output */ BatDev.Output.dataNum = 0; }