/*---------------------------------------------------------------------------*/
int mt_set_gpio_dir_base(unsigned long pin, unsigned long dir)
{
unsigned long bit;
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
if (dir >= GPIO_DIR_MAX)
return -ERINVAL;
/* GPIOERR("before pin:%ld, dir:%ld\n",pin,dir); */
/* pos = pin / MAX_GPIO_REG_BITS; */
bit = DIR_offset[pin].offset;
#ifdef GPIO_BRINGUP
reg = GPIO_RD32(DIR_addr[pin].addr);
if (dir == GPIO_DIR_IN)
reg &= (~(1 << bit));
else
reg |= (1 << bit);
GPIO_WR32(DIR_addr[pin].addr, reg);
#else
if (dir == GPIO_DIR_IN)
GPIO_SET_BITS((1L << bit), DIR_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << bit), DIR_addr[pin].addr + 4);
#endif
/* GPIOERR("%s:pin:%ld, dir:%ld, value:0x%x\n",__FUNCTION__, pin, dir, GPIO_RD32(DIR_addr[pin].addr)); */
return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_pull_enable_base(unsigned long pin, unsigned long enable)
{
unsigned long pos;
unsigned long bit;
unsigned long i,j;
GPIO_REGS *reg = gpio_reg;
/*for special kpad pupd*/
for(i = 0; i < sizeof(kpad_pupd_spec)/sizeof(kpad_pupd_spec[0]); i++) {
if (pin == kpad_pupd_spec[i].pin) {
if (enable == GPIO_PULL_DISABLE) {
GPIO_SET_BITS((3L << (kpad_pupd_spec[i].bit-2)), ®->kpad_ctrl[kpad_pupd_spec[i].reg].rst);
} else {
GPIO_SET_BITS((1L << (kpad_pupd_spec[i].bit-2)), ®->kpad_ctrl[kpad_pupd_spec[i].reg].set);
}
return RSUCCESS;
}
}
if (((pin >= GPIO114)&&(pin <= GPIO119))||((pin >= GPIO99)&&(pin <= GPIO104))||((pin >= GPIO124)&&(pin <= GPIO129))) {
/* msdc IO */
for(i = 0; i < sizeof(msdc_pupd_spec)/sizeof(msdc_pupd_spec[0]); i++) {
for(j = 0; j < sizeof(msdc_pupd_spec[0])/sizeof(msdc_pupd_spec[0][0]); j++) {
if (pin == msdc_pupd_spec[i][j].pin) {
if (enable == GPIO_PULL_DISABLE) {
if (i == 0) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc1_ctrl[msdc_pupd_spec[i][j].reg].rst);
} else if (i == 1) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc2_ctrl[msdc_pupd_spec[i][j].reg].rst);
} else if (i == 2) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc3_ctrl[msdc_pupd_spec[i][j].reg].rst);
}
} else {
if (i == 0) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc1_ctrl[msdc_pupd_spec[i][j].reg].set);
} else if (i == 1) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc2_ctrl[msdc_pupd_spec[i][j].reg].set);
} else if (i == 2) {
GPIO_SET_BITS((3L << (msdc_pupd_spec[i][j].bit - 2)), ®->msdc3_ctrl[msdc_pupd_spec[i][j].reg].set);
}
}
return RSUCCESS;
}
}
}
} else if((pin >= GPIO141)&&(pin <= GPIO166)) {
return GPIO_PULL_EN_UNSUPPORTED;
} else {
pos = pin / MAX_GPIO_REG_BITS;
bit = pin % MAX_GPIO_REG_BITS;
if (enable == GPIO_PULL_DISABLE)
GPIO_SET_BITS((1L << bit), ®->pullen[pos].rst);
else
GPIO_SET_BITS((1L << bit), ®->pullen[pos].set);
}
return RSUCCESS;
}
static void
ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
{
if (ar71xx_soc == AR71XX_SOC_AR9341 ||
ar71xx_soc == AR71XX_SOC_AR9342 ||
ar71xx_soc == AR71XX_SOC_AR9344)
GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
else
GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_out_base(unsigned long pin, unsigned long output)
{
unsigned long pos;
unsigned long bit;
GPIO_REGS *reg = gpio_reg;
pos = pin / MAX_GPIO_REG_BITS;
bit = pin % MAX_GPIO_REG_BITS;
if (output == GPIO_OUT_ZERO)
GPIO_SET_BITS((1L << bit), ®->dout[pos].rst);
else
GPIO_SET_BITS((1L << bit), ®->dout[pos].set);
return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_dir_base(unsigned long pin, unsigned long dir)
{
unsigned long pos;
unsigned long bit;
GPIO_REGS *reg = gpio_reg;
pos = pin / MAX_GPIO_REG_BITS;
bit = pin % MAX_GPIO_REG_BITS;
if (dir == GPIO_DIR_IN)
GPIO_SET_BITS((1L << bit), ®->dir[pos].rst);
else
GPIO_SET_BITS((1L << bit), ®->dir[pos].set);
return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_ies_base(unsigned long pin, unsigned long enable)
{
int i = 0;
GPIO_REGS *reg = gpio_reg;
for(; i < ARRAY_SIZE(mt_ies_smt_map); i++) {
if(pin >= mt_ies_smt_map[i].index_start && pin <= mt_ies_smt_map[i].index_end)
break;
}
if (enable == GPIO_IES_DISABLE)
GPIO_SET_BITS((1L << mt_ies_smt_map[i].bit), ®->ies[mt_ies_smt_map[i].reg_index].rst);
else
GPIO_SET_BITS((1L << mt_ies_smt_map[i].bit), ®->ies[mt_ies_smt_map[i].reg_index].set);
return RSUCCESS;
}
static void
avila_gpio_pin_configure(struct avila_gpio_softc *sc, struct gpio_pin *pin,
unsigned int flags)
{
uint32_t mask;
mask = 1 << pin->gp_pin;
/*
* Manage input/output
*/
if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
IXP4XX_GPIO_LOCK();
pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
if (flags & GPIO_PIN_OUTPUT) {
pin->gp_flags |= GPIO_PIN_OUTPUT;
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOER, mask);
}
else {
pin->gp_flags |= GPIO_PIN_INPUT;
GPIO_SET_BITS(sc, IXP425_GPIO_GPOER, mask);
}
IXP4XX_GPIO_UNLOCK();
}
}
static void
ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
unsigned int flags)
{
uint32_t mask;
mask = 1 << pin->gp_pin;
GPIO_LOCK(sc);
/*
* Manage input/output
*/
if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
if (flags & GPIO_PIN_OUTPUT) {
pin->gp_flags |= GPIO_PIN_OUTPUT;
GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
}
else {
pin->gp_flags |= GPIO_PIN_INPUT;
GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
}
}
GPIO_UNLOCK(sc);
}
static void
ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
{
GPIO_LOCK(sc);
GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
GPIO_UNLOCK(sc);
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_ies_base(unsigned long pin, unsigned long enable)
{
/* unsigned long flags; */
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
if (IES_offset[pin].offset == -1)
return GPIO_IES_UNSUPPORTED;
if (enable == GPIO_IES_DISABLE)
GPIO_SET_BITS((1L << (IES_offset[pin].offset)), IES_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << (IES_offset[pin].offset)), IES_addr[pin].addr + 4);
return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_smt_base(unsigned long pin, unsigned long enable)
{
/* unsigned long flags; */
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
#ifdef GPIO_BRINGUP
if (SMT_offset[pin].offset == -1) {
return GPIO_SMT_UNSUPPORTED;
} else {
bit = SMT_offset[pin].offset;
reg = GPIO_RD32(SMT_addr[pin].addr);
if (enable == GPIO_SMT_DISABLE)
reg &= (~(1 << bit));
else
reg |= (1 << bit);
}
/* printk("SMT addr(%x),value(%x)\n",SMT_addr[pin].addr,GPIO_RD32(SMT_addr[pin].addr)); */
GPIO_WR32(SMT_addr[pin].addr, reg);
#else
if (SMT_offset[pin].offset == -1) {
gpio_smt_unsupport[pin] = -1;
return GPIO_SMT_UNSUPPORTED;
}
if (enable == GPIO_SMT_DISABLE)
GPIO_SET_BITS((1L << (SMT_offset[pin].offset)), SMT_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << (SMT_offset[pin].offset)), SMT_addr[pin].addr + 4);
#endif
/* GPIOERR("%s:pin:%ld, enable:%ld, value:0x%x\n",__FUNCTION__, pin, enable, GPIO_RD32(SMT_addr[pin].addr)); */
return RSUCCESS;
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_pull_enable_base(unsigned long pin, unsigned long enable)
{
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
#ifdef GPIO_BRINGUP
bit = PULLEN_offset[pin].offset;
if (PULLEN_offset[pin].offset == -1)
return GPIO_PULL_EN_UNSUPPORTED;
reg = GPIO_RD32(PULLEN_addr[pin].addr);
if (enable == GPIO_PULL_DISABLE)
reg &= (~(1 << bit));
else
reg |= (1 << bit);
GPIO_WR32(PULLEN_addr[pin].addr, reg);
#else
if (PULLEN_offset[pin].offset == -1) {
gpio_pullen_unsupport[pin] = -1;
return GPIO_PULL_EN_UNSUPPORTED;
}
if (enable == GPIO_PULL_DISABLE)
GPIO_SET_BITS((1L << (PULLEN_offset[pin].offset)),
PULLEN_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << (PULLEN_offset[pin].offset)),
PULLEN_addr[pin].addr + 4);
#endif
return RSUCCESS;
}
static int
avila_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1 << pin;
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask))
return (EINVAL);
IXP4XX_GPIO_LOCK();
if (value)
GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask);
else
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask);
IXP4XX_GPIO_UNLOCK();
return (0);
}
static int
avila_gpio_pin_toggle(device_t dev, uint32_t pin)
{
struct avila_gpio_softc *sc = device_get_softc(dev);
uint32_t mask = 1 << pin;
int res;
if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask))
return (EINVAL);
IXP4XX_GPIO_LOCK();
res = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & mask;
if (res)
GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask);
else
GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask);
IXP4XX_GPIO_UNLOCK();
return (0);
}
/*---------------------------------------------------------------------------*/
int mt_set_gpio_pull_select_base(unsigned long pin, unsigned long select)
{
/* unsigned long flags; */
unsigned long bit = 0;
/*u32 mask = (1L << 4) - 1;*/
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
if (pin == 5) {
pr_err("XXX MSDC SD CD PIN be touched!\n");
dump_stack();
}
#ifdef GPIO_BRINGUP
if (PULL_offset[pin].offset == -1 && pupd_offset[pin].offset == -1)
return GPIO_PULL_UNSUPPORTED;
if (pin >= 160 && pin <= 165) {
bit = pupd_offset[pin].offset;
reg = GPIO_RD32(pupd_addr[pin].addr);
if (select == GPIO_PULL_UP) { /* 0x2 pull up */
reg &= (~(mask << bit));
reg |= (0x2 << bit);
} else { /* 0x6 pull down */
reg &= (~(mask << bit));
reg |= (0x6 << bit);
}
/* printk("fwq pullset pin=%d,3.............\n",pin); */
GPIO_WR32(pupd_addr[pin].addr, reg);
return RSUCCESS;
}
/* printk("fwq pullset pin=%d,select(%d)\n",pin,select); */
if (PULL_offset[pin].offset != -1) {
bit = PULL_offset[pin].offset;
reg = GPIO_RD32(PULL_addr[pin].addr);
if (select == GPIO_PULL_DOWN)
reg &= (~(1 << bit));
else
reg |= (1 << bit);
/* printk("fwq pullset pin=%d,2.............\n",pin); */
GPIO_WR32(PULL_addr[pin].addr, reg);
} else {
bit = pupd_offset[pin].offset + 2;
reg = GPIO_RD32(pupd_addr[pin].addr);
if (select == GPIO_PULL_UP)
reg &= (~(1 << bit));
else
reg |= (1 << bit);
/* printk("fwq pullset pin=%d,3.............\n",pin); */
GPIO_WR32(pupd_addr[pin].addr, reg);
}
#else
if ((PULL_offset[pin].offset == -1) && (pupd_offset[pin].offset == -1)) {
gpio_pull_select_unsupport[pin] = -1;
return GPIO_PULL_UNSUPPORTED;
}
/* printk("fwq pullset pin=%ld,1.............\n",pin); */
if (pin >= 160 && pin <= 165) {
if (select == GPIO_PULL_UP) { /* 0x2 pull up */
/* reg &= (~(mask << bit)); */
/* reg |= (0x2 << bit); */
GPIO_SET_BITS((2L << (pupd_offset[pin].offset)), pupd_addr[pin].addr + 4);
} else { /* 0x6 pull down */
/* reg &= (~(mask << bit)); */
/* reg |= (0x6 << bit); */
GPIO_SET_BITS((6L << (pupd_offset[pin].offset)), pupd_addr[pin].addr + 4);
}
return RSUCCESS;
}
/* printk("fwq pullset pin=%ld,2.............\n",pin); */
/* printk("fwq pullset pin=%d,select(%d)\n",pin,select); */
if (PULL_offset[pin].offset != -1) {
bit = PULL_offset[pin].offset;
/* reg = GPIO_RD32(PULL_addr[pin].addr); */
if (select == GPIO_PULL_DOWN)
GPIO_SET_BITS((1L << bit), PULL_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << bit), PULL_addr[pin].addr + 4);
/* printk("fwq pullset pin=%d,2.............\n",pin); */
} else {
bit = pupd_offset[pin].offset + 2;
/* reg = GPIO_RD32(pupd_addr[pin].addr); */
if (select == GPIO_PULL_UP)
GPIO_SET_BITS((1L << (bit)), pupd_addr[pin].addr + 8);
else
GPIO_SET_BITS((1L << (bit)), pupd_addr[pin].addr + 4);
}
#endif
/* GPIOERR("%s:pin:%ld, select:%ld, value:0x%x\n",__FUNCTION__, pin, select, GPIO_RD32(PULL_addr[pin].addr)); */
return RSUCCESS;
}
