static rt_err_t rt1052_hwtimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
{
rt_err_t err = RT_EOK;
GPT_Type *hwtimer_dev;
hwtimer_dev = (GPT_Type *)timer->parent.user_data;
RT_ASSERT(timer != RT_NULL);
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
uint32_t clk;
uint32_t pre;
clk = EXAMPLE_GPT_CLK_FREQ;
pre = clk / *((uint32_t *)args) - 1;
GPT_SetClockDivider(hwtimer_dev, pre);
}
break;
default:
err = -RT_ENOSYS;
break;
}
return err;
}
void GPT_Init(GPT_Type *base, const gpt_config_t *initConfig)
{
assert(initConfig);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate the GPT clock*/
CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
base->CR = 0U;
GPT_SoftwareReset(base);
base->CR =
(initConfig->enableFreeRun ? GPT_CR_FRR_MASK : 0U) | (initConfig->enableRunInWait ? GPT_CR_WAITEN_MASK : 0U) |
(initConfig->enableRunInStop ? GPT_CR_STOPEN_MASK : 0U) |
(initConfig->enableRunInDoze ? GPT_CR_DOZEEN_MASK : 0U) |
(initConfig->enableRunInDbg ? GPT_CR_DBGEN_MASK : 0U) | (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0U);
GPT_SetClockSource(base, initConfig->clockSource);
GPT_SetClockDivider(base, initConfig->divider);
}
