void usb_stream_reset(struct usb_stream_config const *config)
{
config->out_desc->flags = DOEPDMA_RXBYTES(config->tx_size) |
DOEPDMA_LAST | DOEPDMA_BS_HOST_RDY |
DOEPDMA_IOC;
config->out_desc->addr = config->rx_ram;
GR_USB_DOEPDMA(config->endpoint) = (uint32_t)config->out_desc;
config->in_desc->flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY |
DIEPDMA_IOC;
config->in_desc->addr = config->tx_ram;
GR_USB_DIEPDMA(config->endpoint) = (uint32_t)config->in_desc;
GR_USB_DOEPCTL(config->endpoint) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
DXEPCTL_EPTYPE_BULK |
DXEPCTL_CNAK | DXEPCTL_EPENA;
GR_USB_DIEPCTL(config->endpoint) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
DXEPCTL_EPTYPE_BULK |
DXEPCTL_TXFNUM(config->endpoint);
GR_USB_DAINTMSK |= DAINT_INEP(config->endpoint) |
DAINT_OUTEP(config->endpoint);
*config->is_reset = 1;
/* Flush any queued data */
hook_call_deferred(config->deferred_tx, 0);
hook_call_deferred(config->deferred_rx, 0);
}
/* Change the RX descriptors after each SETUP/OUT packet is received so we can
* prepare to receive another without losing track of this one. */
static void got_RX_packet(void)
{
cur_out_idx = next_out_idx;
cur_out_desc = ep0_out_desc + cur_out_idx;
next_out_idx = (next_out_idx + 1) % NUM_OUT_BUFFERS;
next_out_desc = ep0_out_desc + next_out_idx;
GR_USB_DOEPDMA(0) = (uint32_t)next_out_desc;
}
/* Let the USB HW OUT-from-host FIFO receive some bytes */
static void usb_enable_rx(int len)
{
struct dwc_usb_ep *ep = &ep_console_ctl;
ep->out_data = ep->out_databuffer;
ep->out_pending = 0;
GR_USB_DOEPTSIZ(USB_EP_CONSOLE) = 0;
GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_PKTCNT(1);
GR_USB_DOEPTSIZ(USB_EP_CONSOLE) |= DXEPTSIZ_XFERSIZE(len);
GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)ep->out_data;
GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
}
/* Reset all this to a good starting state. */
static void initialize_dma_buffers(void)
{
int i;
print_later("initialize_dma_buffers()", 0, 0, 0, 0, 0);
for (i = 0; i < NUM_OUT_BUFFERS; i++) {
ep0_out_desc[i].addr = ep0_out_buf[i];
ep0_out_desc[i].flags = DOEPDMA_BS_HOST_BSY;
}
next_out_idx = 0;
next_out_desc = ep0_out_desc + next_out_idx;
GR_USB_DOEPDMA(0) = (uint32_t)next_out_desc;
/* cur_out_* will be updated when we get the first RX packet */
for (i = 0; i < NUM_IN_PACKETS_AT_ONCE; i++) {
ep0_in_desc[i].addr = ep0_in_buf + i * USB_MAX_PACKET_SIZE;
ep0_in_desc[i].flags = DIEPDMA_BS_HOST_BSY;
}
cur_in_desc = ep0_in_desc;
GR_USB_DIEPDMA(0) = (uint32_t)(cur_in_desc);
};
static void ep_reset(void)
{
ep_out_desc.flags = DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE) |
DOEPDMA_LAST | DOEPDMA_BS_HOST_RDY | DOEPDMA_IOC;
ep_out_desc.addr = ep_buf_rx;
GR_USB_DOEPDMA(USB_EP_BLOB) = (uint32_t)&ep_out_desc;
ep_in_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY | DIEPDMA_IOC;
ep_in_desc.addr = ep_buf_tx;
GR_USB_DIEPDMA(USB_EP_BLOB) = (uint32_t)&ep_in_desc;
GR_USB_DOEPCTL(USB_EP_BLOB) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
DXEPCTL_EPTYPE_BULK |
DXEPCTL_CNAK | DXEPCTL_EPENA;
GR_USB_DIEPCTL(USB_EP_BLOB) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
DXEPCTL_EPTYPE_BULK |
DXEPCTL_TXFNUM(USB_EP_BLOB);
GR_USB_DAINTMSK |= (1<<USB_EP_BLOB) | (1 << (USB_EP_BLOB+16));
is_reset = 1;
/* Flush any queued data */
hook_call_deferred(tx_fifo_handler, 0);
hook_call_deferred(rx_fifo_handler, 0);
}
