/* FSMC initialization function */
void MX_FSMC_Init(void)
{
FSMC_NORSRAM_TimingTypeDef Timing;
/** Perform the SRAM1 memory initialization sequence
*/
hsram1.Instance = FSMC_NORSRAM_DEVICE;
hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1.Init */
hsram1.Init.NSBank = FSMC_NORSRAM_BANK1;
hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* Timing */
Timing.AddressSetupTime = 15;
Timing.AddressHoldTime = 15;
Timing.DataSetupTime = 255;
Timing.BusTurnAroundDuration = 15;
Timing.CLKDivision = 16;
Timing.DataLatency = 17;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
HAL_SRAM_Init(&hsram1, &Timing, NULL);
}
void HsramInit (void)
{
hsram.Instance = FSMC_NORSRAM_DEVICE;
hsram.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
SRAM_Timing.AddressSetupTime = 5;
SRAM_Timing.AddressHoldTime = 0;
SRAM_Timing.DataSetupTime = 5;
SRAM_Timing.BusTurnAroundDuration = 0;
SRAM_Timing.CLKDivision = 2;
SRAM_Timing.DataLatency = 0;
SRAM_Timing.AccessMode = FSMC_ACCESS_MODE_A;
hsram.Init.NSBank = FSMC_NORSRAM_BANK1;
hsram.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.WrapMode = FSMC_WRAP_MODE_ENABLE;
hsram.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* Initialize the SRAM controller */
if(HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
}
static int SRAM_Init(void)
{
int result = RT_EOK;
/* SRAM device configuration */
hsram.Instance = FMC_NORSRAM_DEVICE;
hsram.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* SRAM device configuration */
SRAM_Timing.AddressSetupTime = ADDRESSSETUPTIME;
SRAM_Timing.AddressHoldTime = ADDRESSHOLDTIME; /* Min value, Don't care on SRAM Access mode A */
SRAM_Timing.DataSetupTime = DATASETUPTIME;
SRAM_Timing.DataHoldTime = DATAHOLDTIME;
SRAM_Timing.BusTurnAroundDuration = BUSTURNAROUNDDURATION;
SRAM_Timing.CLKDivision = CLKDIVISION; /* Min value, Don't care on SRAM Access mode A */
SRAM_Timing.DataLatency = DATALATENCY; /* Min value, Don't care on SRAM Access mode A */
SRAM_Timing.AccessMode = ACCESSMODE;
hsram.Init.NSBank = FMC_NORSRAM_BANK1;
hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
#if SRAM_DATA_WIDTH == 8
hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_8;
#elif SRAM_DATA_WIDTH == 16
hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
#else
hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_32;
#endif
hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
hsram.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
hsram.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
hsram.Init.NBLSetupTime = 0;
hsram.Init.PageSize = FMC_PAGE_SIZE_NONE;
/* Initialize the SRAM controller */
if (HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK)
{
LOG_E("SRAM init failed!");
result = -RT_ERROR;
}
else
{
LOG_D("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH);
#ifdef RT_USING_MEMHEAP_AS_HEAP
/* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
#endif
}
return result;
}
/**
* @brief Configures the Parallel interface (FSMC) for LCD(Parallel mode)
* @param None
* @retval None
*/
static void LCD_FSMCConfig(void)
{
FSMC_NORSRAM_TimingTypeDef Timing;
/* Enable FSMC clock */
__FSMC_CLK_ENABLE();
/*-- FSMC Configuration ------------------------------------------------------*/
/*----------------------- SRAM Bank 1 ----------------------------------------*/
/* FSMC_NORSRAM_BANK1 configuration */
/* Color LCD configuration ------------------------------------
LCD configured as follow:
- Memory Type = SRAM
- NE1 chip select/ BANK1 (NOR type)
- LCD Register Select A19
- Data/Address MUX = Disable
- Memory Type = SRAM
- Data Width = 16bit
- Write Operation = Enable
- Extended Mode = Enable
- Asynchronous Wait = Disable */
/** Perform the SRAM1 memory initialization sequence
*/
hsram1_ssd2119.Instance = FSMC_NORSRAM_DEVICE;
hsram1_ssd2119.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
/* hsram1_ssd2119.Init */
hsram1_ssd2119.Init.NSBank = FSMC_NORSRAM_BANK1;
hsram1_ssd2119.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram1_ssd2119.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram1_ssd2119.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram1_ssd2119.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram1_ssd2119.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram1_ssd2119.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram1_ssd2119.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram1_ssd2119.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram1_ssd2119.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram1_ssd2119.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram1_ssd2119.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram1_ssd2119.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* Timing */
Timing.AddressSetupTime = 1;
Timing.AddressHoldTime = 1;
Timing.DataSetupTime = 9;
Timing.BusTurnAroundDuration = 0;
Timing.CLKDivision = 0;
Timing.DataLatency = 0;
Timing.AccessMode = FSMC_ACCESS_MODE_A;
/* ExtTiming */
HAL_SRAM_Init(&hsram1_ssd2119, &Timing, NULL);
}
/**
* @brief Initializes the SRAM device.
* @retval SRAM status
*/
uint8_t BSP_SRAM_Init(void)
{
static uint8_t sram_status = SRAM_ERROR;
/* SRAM device configuration */
sramHandle.Instance = FMC_NORSRAM_DEVICE;
sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* SRAM device configuration */
/* Timing configuration derived from system clock (up to 216Mhz)
for 108Mhz as SRAM clock frequency */
Timing.AddressSetupTime = 2;
Timing.AddressHoldTime = 1;
Timing.DataSetupTime = 2;
Timing.BusTurnAroundDuration = 1;
Timing.CLKDivision = 2;
Timing.DataLatency = 2;
Timing.AccessMode = FMC_ACCESS_MODE_A;
sramHandle.Init.NSBank = FMC_NORSRAM_BANK3;
sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
/* SRAM controller initialization */
BSP_SRAM_MspInit(&sramHandle, NULL); /* __weak function can be rewritten by the application */
if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
{
sram_status = SRAM_ERROR;
}
else
{
sram_status = SRAM_OK;
}
return sram_status;
}
/**
* @brief Initializes the SRAM device.
* @param None
* @retval SRAM status
*/
uint8_t BSP_SRAM_Init(void)
{
sramHandle.Instance = FMC_NORSRAM_DEVICE;
sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* SRAM device configuration */
Timing.AddressSetupTime = 2;
Timing.AddressHoldTime = 1;
Timing.DataSetupTime = 2;
Timing.BusTurnAroundDuration = 1;
Timing.CLKDivision = 2;
Timing.DataLatency = 2;
Timing.AccessMode = FMC_ACCESS_MODE_A;
sramHandle.Init.NSBank = FMC_NORSRAM_BANK2;
sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
sramHandle.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
/* SRAM controller initialization */
SRAM_MspInit();
if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
{
return SRAM_ERROR;
}
else
{
return SRAM_OK;
}
}
/**
* @brief Initializes LCD IO.
* @param None
* @retval None
*/
static void STM_FMC_BANK1_Init(void)
{
SRAM_HandleTypeDef hsram;
FMC_NORSRAM_TimingTypeDef SRAM_Timing;
/*** Configure the SRAM Bank 1 ***/
/* Configure IPs */
hsram.Instance = FMC_NORSRAM_DEVICE;
hsram.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
SRAM_Timing.AddressSetupTime = 5;
SRAM_Timing.AddressHoldTime = 1;
SRAM_Timing.DataSetupTime = 9;
SRAM_Timing.BusTurnAroundDuration = 0;
SRAM_Timing.CLKDivision = 2;
SRAM_Timing.DataLatency = 2;
SRAM_Timing.AccessMode = FMC_ACCESS_MODE_A;
hsram.Init.NSBank = FMC_NORSRAM_BANK1;
hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
/* Initialize the SRAM controller */
STM_FMC_BANK1_MspInit();
HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing);
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/* STM32F2xx HAL library initialization:
- Configure the Flash prefetch, instruction and Data caches
- Configure the Systick to generate an interrupt each 1 msec
- Set NVIC Group Priority to 4
- Global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock to 120 MHz */
SystemClock_Config();
/* Configure LED1, LED2 and LED3 */
BSP_LED_Init(LED1);
BSP_LED_Init(LED2);
BSP_LED_Init(LED3);
/*##-1- Configure the SRAM device ##########################################*/
/* SRAM device configuration */
hsram.Instance = FSMC_NORSRAM_DEVICE;
hsram.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
SRAM_Timing.AddressSetupTime = 2;
SRAM_Timing.AddressHoldTime = 1;
SRAM_Timing.DataSetupTime = 2;
SRAM_Timing.BusTurnAroundDuration = 1;
SRAM_Timing.CLKDivision = 2;
SRAM_Timing.DataLatency = 2;
SRAM_Timing.AccessMode = FSMC_ACCESS_MODE_A;
hsram.Init.NSBank = FSMC_NORSRAM_BANK2;
hsram.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
hsram.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
hsram.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
hsram.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
hsram.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
/* Initialize the SRAM controller */
if(HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*##-2- SRAM memory read/write access ######################################*/
/* Fill the buffer to write */
Fill_Buffer(aTxBuffer, BUFFER_SIZE, 0xC20F);
/* Write data to the SRAM memory */
for(uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
*(__IO uint16_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR + 2 * uwIndex) = aTxBuffer[uwIndex];
}
/* Read back data from the SRAM memory */
for(uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
aRxBuffer[uwIndex] = *(__IO uint16_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR + 2 * uwIndex);
}
/*##-3- Checking data integrity ############################################*/
uwWriteReadStatus = Buffercmp(aTxBuffer, aRxBuffer, BUFFER_SIZE);
if(uwWriteReadStatus != PASSED)
{
/* KO */
/* Turn on LED2 */
BSP_LED_On(LED2);
}
else
{
/* OK */
/* Turn on LED1 */
BSP_LED_On(LED1);
}
/* Infinite loop */
while (1)
{
}
}
//------------------------------------------------------------------------------------------------------------------------------------------------------
void FSMC_SetMode(ModeFSMC mode)
{
if (mode != curMode)
{
inSetStateMode = true;
prevMode = curMode;
curMode = mode;
if (curMode == ModeFSMC_Display)
{
/*
static const FMC_NORSRAM_TimingTypeDef sramTiming =
{
5, // FSMC_AddressSetupTime
7, // FSMC_AddressHoldTime
13, // FSMC_DataSetupTime
11, // FSMC_BusTurnAroundDuration
3, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_B // FSMC_AccessMode
};
*/
static const FMC_NORSRAM_TimingTypeDef sramTiming = // WARN временно изменил - возможно, на флешку не пишет из-за неправильных таймингов
{
6, // FSMC_AddressSetupTime
8, // FSMC_AddressHoldTime
14, // FSMC_DataSetupTime
12, // FSMC_BusTurnAroundDuration
3, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_B // FSMC_AccessMode
};
static const SRAM_HandleTypeDef sramHandle =
{
FMC_NORSRAM_DEVICE,
FMC_NORSRAM_EXTENDED_DEVICE,
{
FMC_NORSRAM_BANK1, // Init.NSBank
FMC_DATA_ADDRESS_MUX_ENABLE, // Init.DataAddressMux
FMC_MEMORY_TYPE_NOR, // Init.MemoryType
FMC_NORSRAM_MEM_BUS_WIDTH_8, // Init.MemoryDataWidth
FMC_BURST_ACCESS_MODE_DISABLE, // Init.BurstAccessMode
FMC_WAIT_SIGNAL_POLARITY_LOW, // Init.WaitSignalPolarity
FMC_WRAP_MODE_DISABLE, // Init.WrapMode
FMC_WAIT_TIMING_BEFORE_WS, // Init.WaitSignalActive
FMC_WRITE_OPERATION_ENABLE, // Init.WriteOperation
FMC_WAIT_SIGNAL_DISABLE, // Init.WaitSignal
FMC_EXTENDED_MODE_DISABLE, // Init.ExtendedMode
FMC_ASYNCHRONOUS_WAIT_DISABLE, // Init.AsynchronousWait
FMC_WRITE_BURST_DISABLE // Init.WriteBurst
}
};
if (HAL_SRAM_Init((SRAM_HandleTypeDef*)(&sramHandle), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming)) != HAL_OK)
{
};
}
else if (curMode == ModeFSMC_FPGA)
{
static const FMC_NORSRAM_TimingTypeDef sramTiming =
{
2, // FSMC_AddressSetupTime
4, // FSMC_AddressHoldTime
9, // FSMC_DataSetupTime При значении 9 32кБ записываются в RAM за 1000мкс. Уменьшение
// на одну единцу уменьшает этот параметр на 90 мкс. Если 3 - 32кБ запишутся за 460 мкс.
0, // FSMC_BusTurnAroundDuration
0, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_C // FSMC_AccessMode
};
if (HAL_SRAM_Init((SRAM_HandleTypeDef*)(&gSramHandle), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming)) != HAL_OK)
{
};
}
else if (curMode == ModeFSMC_RAM)
{
static const FMC_NORSRAM_TimingTypeDef sramTimingWrite =
{
1, // FSMC_AddressSetupTime 0...15
1, // FSMC_AddressHoldTime 1...15
7, // FSMC_DataSetupTime 1...255
0, // FSMC_BusTurnAroundDuration 0...15
0, // FSMC_CLKDivision not using
0, // FSMC_DataLatency not using
FMC_ACCESS_MODE_C // FSMC_AccessMode
};
static const FMC_NORSRAM_TimingTypeDef sramTimingRead =
{
1, // FSMC_AddressSetupTime
1, // FSMC_AddressHoldTime
1, // FSMC_DataSetupTime
0, // FSMC_BusTurnAroundDuration
0, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_C // FSMC_AccessMode
};
//HAL_SRAM_DeInit((SRAM_HandleTypeDef*)(&gSramHandle));
if (HAL_SRAM_Init((SRAM_HandleTypeDef*)(&gSramHandle), (FMC_NORSRAM_TimingTypeDef*)(&sramTimingWrite), (FMC_NORSRAM_TimingTypeDef*)(&sramTimingRead)) != HAL_OK)
{
};
}
inSetStateMode = false;
if (funcAfterSetMode)
{
if(funcAfterSetMode())
{
funcAfterSetMode = 0;
}
}
}
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/* STM32F4xx HAL library initialization:
- Configure the Flash prefetch, instruction and Data caches
- Systick timer is configured by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
- Set NVIC Group Priority to 4
- Low Level Initialization: global MSP (MCU Support Package) initialization
*/
HAL_Init();
/* Configure the system clock to 180 MHz */
SystemClock_Config();
/* Configure LED1 and LED3 */
BSP_LED_Init(LED1);
BSP_LED_Init(LED3);
/*##-1- Configure the SRAM device ##########################################*/
/* SRAM device configuration */
hsram.Instance = FMC_NORSRAM_DEVICE;
hsram.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
/* SRAM device configuration */
SRAM_Timing.AddressSetupTime = 2;
SRAM_Timing.AddressHoldTime = 1;
SRAM_Timing.DataSetupTime = 2;
SRAM_Timing.BusTurnAroundDuration = 1;
SRAM_Timing.CLKDivision = 2;
SRAM_Timing.DataLatency = 2;
SRAM_Timing.AccessMode = FMC_ACCESS_MODE_A;
hsram.Init.NSBank = FMC_NORSRAM_BANK2;
hsram.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
hsram.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
hsram.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
hsram.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
hsram.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
hsram.Init.WrapMode = FMC_WRAP_MODE_DISABLE;
hsram.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
hsram.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
hsram.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
hsram.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
hsram.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
hsram.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
HAL_SRAM_DeInit(&hsram);
/* Initialize the SRAM controller */
if(HAL_SRAM_Init(&hsram, &SRAM_Timing, &SRAM_Timing) != HAL_OK)
{
/* Initialization Error */
Error_Handler();
}
/*##-2- SRAM memory read/write access ######################################*/
/* Fill the buffer to write */
Fill_Buffer(aTxBuffer, BUFFER_SIZE, 0xC20FC210);
/* Write data to the SRAM memory */
for(uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
*(__IO uint32_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR + 4 * uwIndex) = aTxBuffer[uwIndex];
}
/* Read back data from the SRAM memory */
for(uwIndex = 0; uwIndex < BUFFER_SIZE; uwIndex++)
{
aRxBuffer[uwIndex] = *(__IO uint32_t *)(SRAM_BANK_ADDR + WRITE_READ_ADDR + 4 * uwIndex);
}
/*##-3- Checking data integrity ############################################*/
uwWriteReadStatus = Buffercmp(aTxBuffer, aRxBuffer, BUFFER_SIZE);
if(uwWriteReadStatus != PASSED)
{
/* KO */
/* Turn on LED3 */
BSP_LED_On(LED3);
}
else
{
/* OK */
/* Turn on LED1 */
BSP_LED_On(LED1);
}
/* Infinite loop */
while (1)
{
}
}
//------------------------------------------------------------------------------------------------------------------------------------------------------
void FSMC_SetMode(ModeFSMC mode)
{
if (mode != curMode)
{
inSetStateMode = true;
prevMode = curMode;
RAM_WaitWriteReadComplete();
curMode = mode;
if (curMode == ModeFSMC_Display)
{
/*
static const FMC_NORSRAM_TimingTypeDef sramTiming =
{
5, // FSMC_AddressSetupTime
7, // FSMC_AddressHoldTime
13, // FSMC_DataSetupTime
11, // FSMC_BusTurnAroundDuration
3, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_B // FSMC_AccessMode
};
*/
static const FMC_NORSRAM_TimingTypeDef sramTiming = // WARN временно изменил - возможно, на флешку не пишет из-за неправильных таймингов
{
6, // FSMC_AddressSetupTime
8, // FSMC_AddressHoldTime
14, // FSMC_DataSetupTime
12, // FSMC_BusTurnAroundDuration
3, // FSMC_CLKDivision
0, // FSMC_DataLatency
FMC_ACCESS_MODE_B // FSMC_AccessMode
};
static const SRAM_HandleTypeDef sramHandle =
{
FMC_NORSRAM_DEVICE,
FMC_NORSRAM_EXTENDED_DEVICE,
{
FMC_NORSRAM_BANK1, // Init.NSBank
FMC_DATA_ADDRESS_MUX_ENABLE, // Init.DataAddressMux
FMC_MEMORY_TYPE_NOR, // Init.MemoryType
FMC_NORSRAM_MEM_BUS_WIDTH_8, // Init.MemoryDataWidth
FMC_BURST_ACCESS_MODE_DISABLE, // Init.BurstAccessMode
FMC_WAIT_SIGNAL_POLARITY_LOW, // Init.WaitSignalPolarity
FMC_WRAP_MODE_DISABLE, // Init.WrapMode
FMC_WAIT_TIMING_BEFORE_WS, // Init.WaitSignalActive
FMC_WRITE_OPERATION_ENABLE, // Init.WriteOperation
FMC_WAIT_SIGNAL_DISABLE, // Init.WaitSignal
FMC_EXTENDED_MODE_DISABLE, // Init.ExtendedMode
FMC_ASYNCHRONOUS_WAIT_DISABLE, // Init.AsynchronousWait
FMC_WRITE_BURST_DISABLE // Init.WriteBurst
}
};
if (HAL_SRAM_Init((SRAM_HandleTypeDef*)(&sramHandle), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming), (FMC_NORSRAM_TimingTypeDef*)(&sramTiming)) != HAL_OK)
{
HARDWARE_ERROR
};
}
else if (curMode == ModeFSMC_FPGA)