int test_hpmaddthread()
{
HPMinit();
int ret = HPMaddThread(0);
if (ret != 0)
return 0;
HPMfinalize();
return 1;
}
int enable_hpm()
{
HPMinit();
HPMaddThread(0);
return 1;
}
int
power_init(int cpuId)
{
uint64_t flags;
int i;
int err;
/* determine Turbo Mode features */
double busSpeed;
power_info.baseFrequency = 0;
power_info.minFrequency = 0;
power_info.turbo.numSteps = 0;
power_info.powerUnit = 0;
power_info.timeUnit = 0;
power_info.hasRAPL = 0;
switch (cpuid_info.model)
{
case SANDYBRIDGE:
case IVYBRIDGE:
case HASWELL:
case SANDYBRIDGE_EP:
case IVYBRIDGE_EP:
case HASWELL_EP:
case ATOM_SILVERMONT_E:
case ATOM_SILVERMONT_Z1:
case ATOM_SILVERMONT_Z2:
case ATOM_SILVERMONT_F:
case BROADWELL:
case BROADWELL_E:
case BROADWELL_D:
power_info.hasRAPL = 1;
break;
case ATOM_SILVERMONT_C:
power_info.hasRAPL = 1;
/* The info_regs list needs an update for Silvermont Type C
because it uses another info register */
info_regs[PKG] = MSR_PKG_POWER_INFO_SILVERMONT;
break;
default:
DEBUG_PLAIN_PRINT(DEBUGLEV_INFO, NO RAPL SUPPORT);
return 0;
break;
}
perfmon_init_maps();
if (!HPMinitialized())
{
HPMaddThread(cpuId);
}
if (power_initialized)
{
return 0;
}
if ( power_info.hasRAPL )
{
busSpeed = 100.0;
}
else
{
busSpeed = 133.33;
}
if (cpuid_info.turbo)
{
err = HPMread(cpuId, MSR_DEV, MSR_PLATFORM_INFO, &flags);
if (err == 0)
{
power_info.baseFrequency = busSpeed * (double) extractBitField(flags,8,8);
power_info.minFrequency = busSpeed * (double) extractBitField((flags>>(32)),8,8);
power_info.turbo.numSteps = cpuid_topology.numCoresPerSocket;
if (cpuid_info.model == WESTMERE_EX)
{
power_info.turbo.numSteps = 4;
}
power_info.turbo.steps = (double*) malloc(power_info.turbo.numSteps * sizeof(double));
if (!power_info.turbo.steps)
{
return -ENOMEM;
}
err = HPMread(cpuId, MSR_DEV, MSR_TURBO_RATIO_LIMIT, &flags);
if (err)
{
fprintf(stderr,"Cannot gather values from MSR_TURBO_RATIO_LIMIT,\n");
}
else
{
for (int i=0; i < power_info.turbo.numSteps; i++)
{
if (i < 8)
{
power_info.turbo.steps[i] = busSpeed * (double) field64(flags,i*8, 8);
}
else
{
power_info.turbo.steps[i] = power_info.turbo.steps[7];
}
}
}
//TODO: Haswell EP and possibly Broadwell EP support multiple turbo
// registers besides MSR_TURBO_RATIO_LIMIT:
// MSR_TURBO_RATIO_LIMIT1 and MSR_TURBO_RATIO_LIMIT2
}
