void
cpuFeatures_init(int cpu)
{
int ret;
uint64_t flags;
ret = HPMread(cpu, MSR_DEV, MSR_IA32_MISC_ENABLE, &flags);
TEST_FLAG(fastStrings,0);
TEST_FLAG(thermalControl,3);
TEST_FLAG(perfMonitoring,7);
TEST_FLAG(branchTraceStorage,11);
TEST_FLAG(pebs,12);
TEST_FLAG(speedstep,16);
TEST_FLAG(monitor,18);
TEST_FLAG(cpuidMaxVal,22);
TEST_FLAG(xdBit,34);
if ((cpuid_info.model == NEHALEM) ||
(cpuid_info.model == NEHALEM_BLOOMFIELD) ||
(cpuid_info.model == NEHALEM_LYNNFIELD) ||
(cpuid_info.model == NEHALEM_WESTMERE) ||
(cpuid_info.model == NEHALEM_WESTMERE_M) ||
(cpuid_info.model == NEHALEM_EX))
{
/*Nehalem */
TEST_FLAG(turboMode,38);
TEST_FLAG(hardwarePrefetcher,9);
TEST_FLAG(clPrefetcher,19);
TEST_FLAG(dcuPrefetcher,37);
TEST_FLAG(ipPrefetcher,39);
}
else if ((cpuid_info.model == CORE2_45) ||
(cpuid_info.model == CORE2_65))
{
/*Core 2*/
TEST_FLAG(hardwarePrefetcher,9);
TEST_FLAG(ferrMultiplex,10);
TEST_FLAG(clPrefetcher,19);
TEST_FLAG(speedstepLock,20);
TEST_FLAG(dcuPrefetcher,37);
TEST_FLAG(dynamicAcceleration,38);
TEST_FLAG(ipPrefetcher,39);
}
/*
printf("FLAGS: 0x%llX \n",flags);
*/
}
void
cpuFeatures_disable(int cpu, CpuFeature type)
{
int ret;
uint64_t flags;
ret = HPMread(cpu, MSR_DEV, MSR_IA32_MISC_ENABLE, &flags);
switch ( type )
{
case HW_PREFETCHER:
printf("HW_PREFETCHER:\t");
flags |= (1ULL<<9);
break;
case CL_PREFETCHER:
printf("CL_PREFETCHER:\t");
flags |= (1ULL<<19);
break;
case DCU_PREFETCHER:
printf("DCU_PREFETCHER:\t");
flags |= (1ULL<<37);
break;
case IP_PREFETCHER:
printf("IP_PREFETCHER:\t");
flags |= (1ULL<<39);
break;
default:
printf("ERROR: CpuFeature not supported!\n");
break;
}
PRINT_VALUE(RED,disabled);
printf("\n");
HPMwrite(cpu, MSR_DEV, MSR_IA32_MISC_ENABLE, flags);
}
void
cpuFeatures_print(int cpu)
{
int ret;
uint64_t flags;
ret = HPMread(cpu, MSR_DEV, MSR_IA32_MISC_ENABLE, &flags);
printf(HLINE);
printf("Fast-Strings: \t\t\t");
if (flags & 1)
{
PRINT_VALUE(GREEN,enabled);
}
else
{
PRINT_VALUE(RED,disabled);
}
printf("Automatic Thermal Control: \t");
if (flags & (1ULL<<3))
{
PRINT_VALUE(GREEN,enabled);
}
else
{
PRINT_VALUE(RED,disabled);
}
printf("Performance monitoring: \t");
if (flags & (1ULL<<7))
{
PRINT_VALUE(GREEN,enabled);
}
else
{
PRINT_VALUE(RED,disabled);
}
printf("Branch Trace Storage: \t\t");
if (flags & (1ULL<<11))
{
PRINT_VALUE(RED,notsupported);
}
else
{
PRINT_VALUE(GREEN,supported);
}
printf("PEBS: \t\t\t\t");
if (flags & (1ULL<<12))
{
PRINT_VALUE(RED,notsupported);
}
else
{
PRINT_VALUE(GREEN,supported);
}
printf("Intel Enhanced SpeedStep: \t");
if (flags & (1ULL<<16))
{
PRINT_VALUE(GREEN,enabled);
}
else
{
PRINT_VALUE(RED,disabled);
}
printf("MONITOR/MWAIT: \t\t\t");
if (flags & (1ULL<<18))
{
PRINT_VALUE(GREEN,supported);
}
else
{
PRINT_VALUE(RED,notsupported);
}
printf("Limit CPUID Maxval: \t\t");
if (flags & (1ULL<<22))
{
PRINT_VALUE(RED,enabled);
}
else
{
PRINT_VALUE(GREEN,disabled);
}
printf("XD Bit Disable: \t\t");
if (flags & (1ULL<<34))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
printf("IP Prefetcher: \t\t\t");
if (flags & (1ULL<<39))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
printf("Hardware Prefetcher: \t\t");
if (flags & (1ULL<<9))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
printf("Adjacent Cache Line Prefetch: \t");
if (flags & (1ULL<<19))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
printf("DCU Prefetcher: \t\t");
if (flags & (1ULL<<37))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
if ((cpuid_info.model == NEHALEM) ||
(cpuid_info.model == NEHALEM_BLOOMFIELD) ||
(cpuid_info.model == NEHALEM_LYNNFIELD) ||
(cpuid_info.model == NEHALEM_WESTMERE) ||
(cpuid_info.model == NEHALEM_WESTMERE_M) ||
(cpuid_info.model == NEHALEM_EX))
{
printf("Intel Turbo Mode: \t");
if (flags & (1ULL<<38))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
}
else if ((cpuid_info.model == CORE2_45) ||
(cpuid_info.model == CORE2_65))
{
printf("Intel Dynamic Acceleration: \t");
if (flags & (1ULL<<38))
{
PRINT_VALUE(RED,disabled);
}
else
{
PRINT_VALUE(GREEN,enabled);
}
}
printf(HLINE);
}
int
power_init(int cpuId)
{
uint64_t flags;
int i;
int err;
/* determine Turbo Mode features */
double busSpeed;
power_info.baseFrequency = 0;
power_info.minFrequency = 0;
power_info.turbo.numSteps = 0;
power_info.powerUnit = 0;
power_info.timeUnit = 0;
power_info.hasRAPL = 0;
switch (cpuid_info.model)
{
case SANDYBRIDGE:
case IVYBRIDGE:
case HASWELL:
case SANDYBRIDGE_EP:
case IVYBRIDGE_EP:
case HASWELL_EP:
case ATOM_SILVERMONT_E:
case ATOM_SILVERMONT_Z1:
case ATOM_SILVERMONT_Z2:
case ATOM_SILVERMONT_F:
case BROADWELL:
case BROADWELL_E:
case BROADWELL_D:
power_info.hasRAPL = 1;
break;
case ATOM_SILVERMONT_C:
power_info.hasRAPL = 1;
/* The info_regs list needs an update for Silvermont Type C
because it uses another info register */
info_regs[PKG] = MSR_PKG_POWER_INFO_SILVERMONT;
break;
default:
DEBUG_PLAIN_PRINT(DEBUGLEV_INFO, NO RAPL SUPPORT);
return 0;
break;
}
perfmon_init_maps();
if (!HPMinitialized())
{
HPMaddThread(cpuId);
}
if (power_initialized)
{
return 0;
}
if ( power_info.hasRAPL )
{
busSpeed = 100.0;
}
else
{
busSpeed = 133.33;
}
if (cpuid_info.turbo)
{
err = HPMread(cpuId, MSR_DEV, MSR_PLATFORM_INFO, &flags);
if (err == 0)
{
power_info.baseFrequency = busSpeed * (double) extractBitField(flags,8,8);
power_info.minFrequency = busSpeed * (double) extractBitField((flags>>(32)),8,8);
power_info.turbo.numSteps = cpuid_topology.numCoresPerSocket;
if (cpuid_info.model == WESTMERE_EX)
{
power_info.turbo.numSteps = 4;
}
power_info.turbo.steps = (double*) malloc(power_info.turbo.numSteps * sizeof(double));
if (!power_info.turbo.steps)
{
return -ENOMEM;
}
err = HPMread(cpuId, MSR_DEV, MSR_TURBO_RATIO_LIMIT, &flags);
if (err)
{
fprintf(stderr,"Cannot gather values from MSR_TURBO_RATIO_LIMIT,\n");
}
else
{
for (int i=0; i < power_info.turbo.numSteps; i++)
{
if (i < 8)
{
power_info.turbo.steps[i] = busSpeed * (double) field64(flags,i*8, 8);
}
else
{
power_info.turbo.steps[i] = power_info.turbo.steps[7];
}
}
}
//TODO: Haswell EP and possibly Broadwell EP support multiple turbo
// registers besides MSR_TURBO_RATIO_LIMIT:
// MSR_TURBO_RATIO_LIMIT1 and MSR_TURBO_RATIO_LIMIT2
}
