示例#1
0
DIB pas_dib = { d_PAS, -1, v_PAS, pas_tplte, &pas, &pas_ini };

UNIT pas_unit = { UDATA (&pasi_svc, UNIT_ATTABLE|UNIT_IDLE, 0), 0 };

REG pas_reg[] = {
    { BRDATA (STA, pas_sta, 16, 8, PAS_LINES) },
    { BRDATA (CMD, pas_cmd, 16, 16, PAS_LINES) },
    { BRDATA (RBUF, pas_rbuf, 16, 8, PAS_LINES) },
    { BRDATA (XBUF, pas_xbuf, 16, 8, PAS_LINES) },
    { BRDATA (IREQ, &int_req[l_PAS], 16, 32, PAS_LINES / 16) },
    { BRDATA (IENB, &int_enb[l_PAS], 16, 32, PAS_LINES / 16) },
    { BRDATA (RARM, pas_rarm, 16, 1, PAS_LINES) },
    { BRDATA (XARM, pas_xarm, 16, 1, PAS_LINES) },
    { BRDATA (RCHP, pas_rchp, 16, 1, PAS_LINES) },
    { HRDATA (DEVNO, pas_dib.dno, 8), REG_HRO },
    { NULL }
    };

MTAB pas_mod[] = {
    { MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
      &tmxr_dscln, NULL, (void *) &pas_desc },
    { UNIT_ATT, UNIT_ATT, "summary", NULL,
      NULL, &tmxr_show_summ, (void *) &pas_desc },
    { MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
      NULL, &tmxr_show_cstat, (void *) &pas_desc },
    { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
      NULL, &tmxr_show_cstat, (void *) &pas_desc },
    { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
      &set_dev, &show_dev, NULL },
    { MTAB_XTD | MTAB_VDV, 0, "LINES", "LINES",
示例#2
0
t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);

extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
extern int32 eval_int (void);

/* SBIA data structures

   sbia_dev     SBIA device descriptor
   sbia_unit    SBIA unit
   sbia_reg     SBIA register list
*/

UNIT sbia_unit = { UDATA (NULL, 0, 0) };

REG sbia_reg[] = {
    { HRDATA (NREQ14, nexus_req[0], 16) },
    { HRDATA (NREQ15, nexus_req[1], 16) },
    { HRDATA (NREQ16, nexus_req[2], 16) },
    { HRDATA (NREQ17, nexus_req[3], 16) },
    { HRDATA (SBIFS, sbi_fs, 32) },
    { HRDATA (SBISC, sbi_sc, 32) },
    { HRDATA (SBIMT, sbi_mt, 32) },
    { HRDATA (SBIER, sbi_er, 32) },
    { HRDATA (SBITMO, sbi_tmo, 32) },
    { HRDATA (SBICSR, sbi_csr, 32) },
    { NULL }
    };

DEVICE sbia_dev = {
    "SBIA", &sbia_unit, sbia_reg, NULL,
    1, 16, 16, 1, 16, 8,
示例#3
0
文件: lgp_cpu.c 项目: BillHeaton/simh
extern t_stat op_i (uint32 dev, uint32 ch, uint32 sh4);
extern void lgp_vm_init (void);

/* CPU data structures

   cpu_dev      CPU device descriptor
   cpu_unit     CPU unit descriptor
   cpu_reg      CPU register list
   cpu_mod      CPU modifiers list
*/

UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_IN4B+UNIT_TTSS_D, MEMSIZE) };

REG cpu_reg[] = {
    { DRDATA (C, PC, 12), REG_VMAD },
    { HRDATA (A, A, 32), REG_VMIO },
    { HRDATA (IR, IR, 32), REG_VMIO },
    { FLDATA (OVF, OVF, 0) },
    { FLDATA (TSW, t_switch, 0) },
    { FLDATA (BP32, bp32, 0) },
    { FLDATA (BP16, bp16, 0) },
    { FLDATA (BP8, bp8, 0) },
    { FLDATA (BP4, bp4, 0) },
    { FLDATA (INPST, inp_strt, 0) },
    { FLDATA (INPDN, inp_done, 0) },
    { FLDATA (OUTST, out_strt, 0) },
    { FLDATA (OUTDN, out_done, 0) },
    { DRDATA (DELAY, delay, 7) },
    { BRDATA (CQ, pcq, 16, 12, PCQ_SIZE), REG_RO + REG_CIRC },
    { HRDATA (CQP, pcq_p, 6), REG_HRO },
    { HRDATA (WRU, sim_int_char, 8) },
示例#4
0
t_stat ttp_reset (DEVICE *dptr);
t_stat ttp_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat ttp_set_break (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat ttp_set_enbdis (UNIT *uptr, int32 val, char *cptr, void *desc);

/* TTP data structures */

DIB ttp_dib = { d_TTP, -1, v_TTP, ttp_tplte, &ttp, NULL };

UNIT ttp_unit[] = {
    { UDATA (&ttpi_svc, UNIT_IDLE, 0), 0 },
    { UDATA (&ttpo_svc, 0, 0), SERIAL_OUT_WAIT }
    };

REG ttp_reg[] = {
    { HRDATA (CMD, ttp_cmd, 16) },
    { HRDATA (KBUF, ttp_unit[TTI].buf, 8) },
    { DRDATA (KPOS, ttp_unit[TTI].pos, T_ADDR_W), PV_LEFT },
    { DRDATA (KTIME, ttp_unit[TTI].wait, 24), REG_NZ + PV_LEFT + REG_HRO },
    { FLDATA (KIREQ, int_req[l_TTP], i_TTP) },
    { FLDATA (KIENB, int_enb[l_TTP], i_TTP) },
    { FLDATA (KARM, ttp_karm, 0) },
    { FLDATA (CHP, ttp_kchp, 0) },
    { HRDATA (TBUF, ttp_unit[TTO].buf, 8) },
    { DRDATA (TPOS, ttp_unit[TTO].pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TTIME, ttp_unit[TTO].wait, 24), REG_NZ + PV_LEFT },
    { FLDATA (TIREQ, int_req[l_TTP], i_TTP + 1) },
    { FLDATA (TIENB, int_enb[l_TTP], i_TTP + 1) },
    { FLDATA (TARM, ttp_tarm, 0) },
    { HRDATA (DEVNO, ttp_dib.dno, 8), REG_HRO },
    { NULL }
示例#5
0
文件: id_dp.c 项目: B-Rich/simh
DIB dp_dib = { d_DPC, 0, v_DPC, dp_tplte, &dp, &dp_ini };

UNIT dp_unit[] = {
    { UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
             UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) },
    { UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
             UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) },
    { UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
             UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) },
    { UDATA (&dp_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
             UNIT_ROABLE+(TYPE_5440 << UNIT_V_DTYPE), SIZE_5440) }
    };

REG dp_reg[] = {
    { HRDATA (CMD, dp_cmd, 3) },
    { HRDATA (STA, dp_sta, 8) },
    { HRDATA (BUF, dp_db, 8) },
    { HRDATA (PLAT, dp_plat, 1) },
    { HRDATA (HDSC, dp_hdsc, 6) },
    { HRDATA (CYL, dp_cyl, 9) },
    { HRDATA (SVUN, dp_svun, 8), REG_HIDDEN },
    { BRDATA (DBUF, dpxb, 16, 8, DP_NUMBY) },
    { HRDATA (DBPTR, dp_bptr, 9), REG_RO },
    { FLDATA (FIRST, dp_1st, 0) },
    { GRDATA (IREQ, int_req[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
    { GRDATA (IENB, int_enb[l_DPC], 16, DP_NUMDR + 1, i_DPC) },
    { BRDATA (IARM, dpd_arm, 16, 1, DP_NUMDR) },
    { DRDATA (RTIME, dp_rtime, 0), PV_LEFT | REG_NZ },
    { DRDATA (STIME, dp_stime, 0), PV_LEFT | REG_NZ },
    { DRDATA (WTIME, dp_wtime, 0), PV_LEFT | REG_NZ },
示例#6
0
    "TODR", &clk_unit, clk_reg, NULL,
    1, 0, 8, 4, 0, 32,
    NULL, NULL, &clk_reset,
    NULL, &clk_attach, &clk_detach,
    NULL, 0, 0, NULL, NULL, NULL, &clk_help, NULL, NULL, 
    &clk_description
    };

UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) };                     /* timer */

REG tmr_reg[] = {
    { HRDATAD (ICCS,          tmr_iccs, 32, "interval timer control and status") },
    { HRDATAD (ICR,            tmr_icr, 32, "interval count register") },
    { HRDATAD (NICR,          tmr_nicr, 32, "next interval count register") },
    { FLDATAD (INT,            tmr_int,  0, "interrupt request") },
    { HRDATA  (INCR,           tmr_inc, 32), REG_HIDDEN },
    { HRDATA  (SAVE,           tmr_sav, 32), REG_HIDDEN },
    { NULL }
    };

DEVICE tmr_dev = {
    "TMR", &tmr_unit, tmr_reg, NULL,
    1, 0, 0, 0, 0, 0,
    NULL, NULL, &tmr_reset,
    NULL, NULL, NULL,
    NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, 
    &tmr_description
    };

/* RX01 data structures
示例#7
0
static t_stat (*mbregW[MBA_NUM])(int32 dat, int32 ad, int32 md);
static int32 (*mbabort[MBA_NUM])(void);

/* Massbus adapter data structures

   mba_dev      MBA device descriptors
   mbax_unit    MBA unit
   mbax_reg     MBA register list
*/

DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) };

UNIT mba0_unit = { UDATA (NULL, 0, 0) };

REG mba0_reg[] = {
    { HRDATA (CNFR, mba_cnf[0], 32) },
    { HRDATA (CR, mba_cr[0], 4) },
    { HRDATA (SR, mba_sr[0], 32) },
    { HRDATA (VA, mba_va[0], 17) },
    { HRDATA (BC, mba_bc[0], 16) },
    { HRDATA (DR, mba_dr[0], 32) },
    { HRDATA (SMR, mba_dr[0], 32) },
    { BRDATA (MAP, mba_map[0], 16, 32, MBA_NMAPR) },
    { FLDATA (NEXINT, nexus_req[IPL_MBA0], TR_MBA0) },
    { NULL }
    };

MTAB mba0_mod[] = {
    { MTAB_XTD|MTAB_VDV, TR_MBA0, "NEXUS", NULL,
      NULL, &show_nexus },
    { 0 }
示例#8
0
extern int32 sysd_hlt_enb (void);
extern int32 fault_PC;

/* TTI data structures

   tti_dev      TTI device descriptor
   tti_unit     TTI unit descriptor
   tti_reg      TTI register list
*/

DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };

UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };

REG tti_reg[] = {
    { HRDATA (BUF, tti_unit.buf, 16) },
    { HRDATA (CSR, tti_csr, 16) },
    { FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
    { FLDATA (DONE, tti_csr, CSR_V_DONE) },
    { FLDATA (IE, tti_csr, CSR_V_IE) },
    { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
    { NULL }
    };

MTAB tti_mod[] = {
    { TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
    { TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
    { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
      NULL, &show_vec, NULL },
    { 0 }
示例#9
0
static t_stat scp300f_reset(DEVICE *scp300f_dev);

static uint8 SCP300F_Read(const uint32 Addr);
static uint8 SCP300F_Write(const uint32 Addr, uint8 cData);

static int32 scp300fdev(const int32 port, const int32 io, const int32 data);
static int32 scp300f_mem(const int32 port, const int32 io, const int32 data);

static int32 scp300f_sr = 0x00;     /* Sense Switch Register, 0=Monitor prompt, 1=disk boot */

static UNIT scp300f_unit[] = {
    { UDATA (NULL, UNIT_FIX + UNIT_DISABLE, 0) }
};

static REG scp300f_reg[] = {
    { HRDATA (SR,           scp300f_sr,     8), },
    { NULL }
};

static MTAB scp300f_mod[] = {
    { MTAB_XTD|MTAB_VDV,    0,                      "MEMBASE",  "MEMBASE",  &set_membase, &show_membase, NULL },
    { MTAB_XTD|MTAB_VDV,    0,                      "IOBASE",   "IOBASE",   &set_iobase, &show_iobase, NULL },
    /* quiet, no warning messages       */
    { UNIT_SCP300F_VERBOSE, 0,                      "QUIET",    "QUIET",    NULL },
    /* verbose, show warning messages   */
    { UNIT_SCP300F_VERBOSE, UNIT_SCP300F_VERBOSE,   "VERBOSE",  "VERBOSE",  NULL },
    { 0 }
};

#define TRACE_PRINT(level, args)    if(scp300f_dev.dctrl & level) { \
                                       printf args;                 \
示例#10
0
uint8 dskbuf[SECT_SIZE];			/* Data Buffer */
UNIT *dptr = NULL;					/* fileref to write dirty buffer to */
int32 fdcbyte;
int32 intrq = 0;					/* interrupt request flag */

/* DC-4 Simh Device Data Structures */

UNIT dsk_unit[] = {
	{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE)  },
	{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE)  },
	{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE)  },
	{ UDATA (&dsk_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE, DSK_SIZE)  } };

REG dsk_reg[] = {
	{ HRDATA (DISK, cur_dsk, 4) },
	{ NULL } };

MTAB dsk_mod[] = {
	{ UNIT_ENABLE, UNIT_ENABLE, "RW", "RW", NULL },
	{ UNIT_ENABLE, 0, "RO", "RO", NULL },
	{ 0 } };

DEVICE dsk_dev = {
	"DSK", dsk_unit, dsk_reg, dsk_mod,
	NUM_DISK, 16, 16, 1, 16, 8,
	NULL, NULL, &dsk_reset,
	NULL, NULL, NULL };

/* service routines to handle simlulator functions */
示例#11
0
文件: pcbus.c 项目: pkoning2/simh
extern t_stat SBC_reset(DEVICE *dptr);      /* reset the PC XT simulator */
extern void set_cpuint(int32 int_num);

/* external globals */

extern int32 int_req;                       /* i8088 INT signal */
extern uint16 port;                         //port called in dev_table[port]

/* Standard SIMH Device Data Structures */

UNIT xtbus_unit = { 
    UDATA (&xtbus_svc, 0, 0), 20 
};

REG xtbus_reg[] = { 
    { HRDATA (MBIRQ, mbirq, 32) }, 
};

DEBTAB xtbus_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }
};

DEVICE xtbus_dev = {
    "PCBUS",                    //name 
    &xtbus_unit,             //units 
示例#12
0
int32 int_vec[IPL_HLVL][32];                            /* int req to vector */

/* Unibus adapter data structures

   uba_dev      UBA device descriptor
   uba_unit     UBA units
   uba_reg      UBA register list
*/

DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };

UNIT uba_unit = { UDATA (&uba_svc, 0, 0) };

REG uba_reg[] = {
    { HRDATA (IPL14, int_req[0], 32), REG_RO },
    { HRDATA (IPL15, int_req[1], 32), REG_RO },
    { HRDATA (IPL16, int_req[2], 32), REG_RO },
    { HRDATA (IPL17, int_req[3], 32), REG_RO },
    { HRDATA (CNFR, uba_cnf, 32) },
    { HRDATA (CR, uba_cr, 32) },
    { HRDATA (SR, uba_sr, 32) },
    { HRDATA (DR, uba_dr, 32) },
    { FLDATA (INT, uba_int, 0) },
    { FLDATA (NEXINT, nexus_req[IPL_UBA], TR_UBA) },
    { FLDATA (AIIP, uba_aiip, 0) },
    { FLDATA (UIIP, uba_uiip, 0) },
    { HRDATA (FMER, uba_fmer, 32) },
    { HRDATA (FUBAR, uba_fubar, 32) },
    { HRDATA (BRSVR0, uba_svr[0], 32) },
    { HRDATA (BRSVR1, uba_svr[1], 32) },
示例#13
0
文件: pata.c 项目: B-Rich/simh
#include "system_defs.h"

extern int32 reg_dev(int32 (*routine)(), int32 port);

/* function prototypes */

t_stat pata_reset (DEVICE *dptr, int32 base);

/* i8255 Standard I/O Data Structures */

UNIT pata_unit[] = {
    { UDATA (0, 0, 0) }
};

REG pata_reg[] = {
    { HRDATA (CONTROL0, pata_unit[0].u3, 8) },
    { HRDATA (PORTA0, pata_unit[0].u4, 8) },
    { HRDATA (PORTB0, pata_unit[0].u5, 8) },
    { HRDATA (PORTC0, pata_unit[0].u6, 8) },
    { NULL }
};

DEVICE pata_dev = {
    "PATA",             //name
    pata_unit,         //units
    pata_reg,          //registers
    NULL,               //modifiers
    1,                  //numunits
    16,                 //aradix
    32,                 //awidth
    1,                  //aincr
示例#14
0
文件: s3_pkb.c 项目: BillHeaton/simh
#define KBD_PROLIGHT 0x10                               /* Proceed indicator (light on/off) */
#define KBD_REQINT 0x04                                 /* Req key interrupts enabled */
#define KBD_KEYINT 0x02                                 /* Other key interrupts enabled */
#define PRT_PRTINT 0x01                                 /* Printer interrupts enabled */

/* Keys mapped to 5471 functions */

int32 key_req = 0x01;                                   /* Request key: ^A */
int32 key_rtn = 0x12;                                   /* Return key: ^R */
int32 key_can = 0x1B;                                   /* Cancel key: ESC */
int32 key_end = 0x0d;                                   /* End key - CR */

UNIT pkb_unit = { UDATA (&pkb_svc, 0, 0), KBD_POLL_WAIT };

REG pkb_reg[] = {
    { HRDATA (FLAG, pkb_unit.u3, 16) },
    { HRDATA (IBUF, pkb_unit.buf, 8) },
    { HRDATA (OBUF, pkb_unit.u4, 8) },
    { HRDATA (REQKEY, key_req, 8) },
    { HRDATA (RTNKEY, key_rtn, 8) },
    { HRDATA (CANKEY, key_can, 8) },
    { HRDATA (ENDKEY, key_end, 8) },
    { DRDATA (POS, pkb_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, pkb_unit.wait, 24), REG_NZ + PV_LEFT },
    { NULL }
};

MTAB pkb_mod[] = {
    { 0 }
};
示例#15
0
文件: ioc-cont.c 项目: pkoning2/simh
uint8 ioc_cont(t_bool io, uint8 data, uint8 devnum);    /* ioc_cont*/
t_stat ioc_cont_reset (DEVICE *dptr, uint16 base, uint8 devnum);

/* external function prototypes */

extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);
extern uint32 saved_PC;                    /* program counter */

/* globals */

UNIT ioc_cont_unit[] = {
    { UDATA (0, 0, 0) },                /* ioc_cont*/
};

REG ioc_cont_reg[] = {
    { HRDATA (CONTROL0, ioc_cont_unit[0].u3, 8) }, /* ioc_cont */
    { NULL }
};

DEBTAB ioc_cont_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "XACK", DEBUG_xack },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }
};

/* address width is set to 16 bits to use devices in 8086/8088 implementations */
示例#16
0
static t_stat ptp_svc    (UNIT *uptr);
static t_stat ptp_reset  (DEVICE *dptr);
static t_stat ptp_attach (UNIT *uptr, char *cptr);
static t_stat ptp_detach (UNIT *uptr);

static int16 ptr_dsw   = 0;								/* device status word */
static int32 ptr_wait  = 1000;							/* character read wait */
static uint8 ptr_char  = 0;								/* last character read */
static int32 ptp_wait  = 1000;							/* character punch wait */

UNIT ptr_unit[1] = {
	{ UDATA (&ptr_svc, UNIT_ATTABLE, 0) },
};

REG ptr_reg[] = {
	{ HRDATA (DSW, 	    ptr_dsw,  16) },				/* device status word */
	{ DRDATA (WTIME,    ptr_wait, 24), PV_LEFT },		/* character read wait */
	{ DRDATA (LASTCHAR, ptr_char,  8), PV_LEFT },		/* last character read */
	{ NULL }  };

DEVICE ptr_dev = {
	"PTR", ptr_unit, ptr_reg, NULL,
	1, 16, 16, 1, 16, 16,
	NULL, NULL, ptr_reset,
	ptr_boot, ptr_attach, ptr_detach};

UNIT ptp_unit[1] = {
	{ UDATA (&ptp_svc, UNIT_ATTABLE, 0) },
};

REG ptp_reg[] = {
示例#17
0
文件: i1620_lp.c 项目: ST3ALth/simh
/* LPT data structures

   lpt_dev      LPT device descriptor
   lpt_unit     LPT unit descriptor
   lpt_reg      LPT register list
*/

UNIT lpt_unit = {
    UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_TEXT, 50)
    };

REG lpt_reg[] = {
    { BRDATA (LBUF, lpt_buf, 8, 8, LPT_BSIZE + 1) },
    { DRDATA (BPTR, lpt_bptr, 8) },
    { HRDATA (PCTL, lpt_savctrl, 8) },
    { FLDATA (PRCHK, ind[IN_PRCHK], 0) },
    { FLDATA (PRCH9, ind[IN_PRCH9], 0) },
    { FLDATA (PRCH12, ind[IN_PRCH12], 0) },
    { FLDATA (PRBSY, ind[IN_PRBSY], 0) },
    { DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
    { BRDATA (CCT, cct, 8, 32, CCT_LNT) },
    { DRDATA (CCTP, cct_ptr, 8), PV_LEFT },
    { DRDATA (CCTL, cct_lnt, 8), REG_RO + PV_LEFT },
    { NULL }
    };

DEVICE lpt_dev = {
    "LPT", &lpt_unit, lpt_reg, NULL,
    1, 10, 31, 1, 8, 7,
    NULL, NULL, &lpt_reset,
示例#18
0
文件: isbc202.c 项目: simh/simh
    uint8   rbyte1;                     //FDC result byte for type 10
    uint8   intff;                      //fdc interrupt FF
    FDDDEF  fdd[FDD_NUM];               //indexed by the FDD number
}    FDCDEF;

FDCDEF    fdc202[4];                    //indexed by the isbc-202 instance number

UNIT isbc202_unit[] = {
    { UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
    { UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
    { UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 },
    { UDATA (0, UNIT_ATTABLE+UNIT_DISABLE, 0), 20 }
};

REG isbc202_reg[] = {
    { HRDATA (STAT0, fdc202[0].stat, 8) },      /* isbc202 0 status */
    { HRDATA (RTYP0, fdc202[0].rtype, 8) },     /* isbc202 0 result type */
    { HRDATA (RBYT0A, fdc202[0].rbyte0, 8) },   /* isbc202 0 result byte 0 */
    { HRDATA (RBYT0B, fdc202[0].rbyte1, 8) },   /* isbc202 0 result byte 1 */
    { HRDATA (INTFF0, fdc202[0].intff, 8) },    /* isbc202 0 interrupt f/f */
    { HRDATA (STAT1, fdc202[1].stat, 8) },      /* isbc202 1 status */
    { HRDATA (RTYP1, fdc202[1].rtype, 8) },     /* isbc202 1 result type */
    { HRDATA (RBYT1A, fdc202[1].rbyte0, 8) },   /* isbc202 1 result byte 0 */
    { HRDATA (RBYT1B, fdc202[1].rbyte1, 8) },   /* isbc202 1 result byte 1 */
    { HRDATA (INTFF1, fdc202[1].intff, 8) },    /* isbc202 1 interrupt f/f */
    { HRDATA (STAT2, fdc202[2].stat, 8) },      /* isbc202 2 status */
    { HRDATA (RTYP2, fdc202[2].rtype, 8) },     /* isbc202 2 result type */
    { HRDATA (RBYT2A, fdc202[2].rbyte0, 8) },   /* isbc202 2 result byte 0 */
    { HRDATA (RBYT2B, fdc202[0].rbyte1, 8) },   /* isbc202 2 result byte 1 */
    { HRDATA (INTFF2, fdc202[2].intff, 8) },    /* isbc202 2 interrupt f/f */
    { HRDATA (STAT3, fdc202[3].stat, 8) },      /* isbc202 3 status */
示例#19
0
/* These are needed for DMA. */
extern void PutByteDMA(const uint32 Addr, const uint32 Value);
extern uint8 GetByteDMA(const uint32 Addr);

static t_stat selchan_reset(DEVICE *selchan_dev);

static int32 selchandev(const int32 port, const int32 io, const int32 data);


static UNIT selchan_unit[] = {
    { UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }
};

static REG selchan_reg[] = {
    { HRDATA (DMA_MODE,    selchan_info_data.dma_mode,    8), },
    { HRDATA (DMA_ADDR,    selchan_info_data.dma_addr,    24), },
    { NULL }
};

static MTAB selchan_mod[] = {
    { MTAB_XTD|MTAB_VDV,    0,                      "IOBASE",   "IOBASE",   &set_iobase, &show_iobase, NULL },
    /* quiet, no warning messages       */
    { UNIT_SELCHAN_VERBOSE, 0,                      "QUIET",    "QUIET",    NULL },
    /* verbose, show warning messages   */
    { UNIT_SELCHAN_VERBOSE, UNIT_SELCHAN_VERBOSE,   "VERBOSE",  "VERBOSE",  NULL },
    { 0 }
};

#define TRACE_PRINT(level, args)    if(selchan_dev.dctrl & level) { \
                                       printf args;                 \
示例#20
0
文件: id_lp.c 项目: ST3ALth/simh
t_stat lpt_vfu (UNIT *uptr, int32 ch);
t_stat lpt_spc (UNIT *uptr, int32 cnt);

/* LPT data structures

   lpt_dev      LPT device descriptor
   lpt_unit     LPT unit descriptors
   lpt_reg      LPT register list
*/

DIB lpt_dib = { d_LPT, -1, v_LPT, NULL, &lpt, NULL };

UNIT lpt_unit = { UDATA (&lpt_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_UC+UNIT_TEXT, 0) };

REG lpt_reg[] = {
    { HRDATA (STA, lpt_sta, 8) },
    { HRDATA (BUF, lpt_unit.buf, 7) },
    { BRDATA (DBUF, lpxb, 16, 7, LPT_WIDTH) },
    { HRDATA (DBPTR, lpt_bptr, 8) },
    { HRDATA (VFUP, lpt_vfup, 8) },
    { HRDATA (VFUL, lpt_vful, 8) },
    { BRDATA (VFUT, lpt_vfut, 16, 8, VFU_LNT) },
    { FLDATA (IREQ, int_req[l_LPT], i_LPT) },
    { FLDATA (IENB, int_enb[l_LPT], i_LPT) },
    { FLDATA (IARM, lpt_arm, 0) },
    { DRDATA (POS, lpt_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (CTIME, lpt_ctime, 24), PV_LEFT },
    { DRDATA (STIME, lpt_stime, 24), PV_LEFT },
    { FLDATA (STOP_IOE, lpt_stopioe, 0) },
    { HRDATA (DEVNO, lpt_dib.dno, 8), REG_HRO },
    { NULL }
示例#21
0
文件: multibus.c 项目: ST3ALth/simh
extern t_stat isbc064_reset (DEVICE *dptr);
extern t_stat isbc208_reset (DEVICE *dptr);

/* external globals */

extern uint8 xack;                          /* XACK signal */
extern int32 int_req;                       /* i8080 INT signal */

/* multibus Standard SIMH Device Data Structures */

UNIT multibus_unit = { 
    UDATA (&multibus_svc, 0, 0), 20 
};

REG multibus_reg[] = { 
    { HRDATA (MBIRQ, mbirq, 32) }, 
    { HRDATA (XACK, xack, 8) }
};

DEBTAB multibus_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }
};

DEVICE multibus_dev = {
    "MBIRQ",                    //name 
示例#22
0
uint32 lp_print (UNIT *uptr);

/* LP data structures

   lp_dev       LP device descriptor
   lp_unit      LP unit descriptors
   lp_reg       LP register list
   lp_mod       LP modifiers list
*/

dib_t lp_dib = { DVA_LP, lp_disp, 0, NULL };

UNIT lp_unit = { UDATA (&lp_svc, UNIT_ATTABLE+UNIT_SEQ, 0), SERIAL_OUT_WAIT };

REG lp_reg[] = {
    { HRDATA (CMD, lp_cmd, 9) },
    { BRDATA (BUF, lp_buf, 16, 7, BUF_LNT4) },
    { FLDATA (PASS, lp_pass, 0) },
    { FLDATA (INH, lp_inh, 0) },
    { FLDATA (RUNAWAY, lp_run, LPDV_V_RUN) },
    { BRDATA (CCT, lp_cct, 8, 8, CCT_LNT) },
    { DRDATA (CCTP, lp_cctp, 8), PV_LEFT },
    { DRDATA (CCTL, lp_cctl, 8), PV_LEFT + REG_HRO + REG_NZ },
    { DRDATA (POS, lp_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, lp_unit.wait, 24), PV_LEFT },
    { FLDATA (STOP_IOE, lp_stopioe, 0) },
    { HRDATA (LASTC, lp_lastcmd, 8), REG_HIDDEN },
    { FLDATA (MODEL, lp_model, 0), REG_HRO },
    { HRDATA (DEVNO, lp_dib.dva, 12), REG_HRO },
    { NULL }
    };
示例#23
0
文件: sigma_mt.c 项目: ProtoSD/simh
    { UDATA (&mtu_svc, UNIT_ATTABLE+UNIT_ROABLE+UNIT_DISABLE, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) },
    { UDATA (&mtr_svc, UNIT_DIS, 0) }
    };

REG mt_reg[] = {
    { BRDATA (BUF, mt_xb, 16, 8, MT_MAXFR) },
    { DRDATA (BPTR, mt_bptr, 17) },
    { DRDATA (BLNT, mt_blim, 17) },
    { HRDATA (RWINT, mt_rwi, MT_NUMDR) },
    { DRDATA (TIME, mt_time, 24), PV_LEFT+REG_NZ },
    { DRDATA (CTIME, mt_ctime, 24), PV_LEFT+REG_NZ },
    { DRDATA (RWTIME, mt_rwtime, 24), PV_LEFT+REG_NZ },
    { URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
    { URDATA (UCMD, mt_unit[0].UCMD, 16, 8, 0, 2 * MT_NUMDR, 0) },
    { URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
              MT_NUMDR, PV_LEFT | REG_RO) },
    { FLDATA (STOP_IOE, mt_stopioe, 0) },
    { HRDATA (DEVNO, mt_dib.dva, 12), REG_HRO },
    { NULL }
    };

MTAB mt_mod[] = {
    { MTUF_WLK, 0, "write enabled", "WRITEENABLED", NULL },
    { MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL }, 
示例#24
0
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern int32 eval_int (void);

/* SYSD data structures

   sysd_dev     SYSD device descriptor
   sysd_unit    SYSD units
   sysd_reg     SYSD register list
*/

UNIT sysd_unit = { UDATA (NULL, 0, 0) };

REG sysd_reg[] = {
    { HRDATA (CONISP, conisp, 32) },
    { HRDATA (CONPC, conpc, 32) },
    { HRDATA (CONPSL, conpsl, 32) },
    { BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO },
    { NULL }
    };

DEVICE sysd_dev = {
    "SYSD", &sysd_unit, sysd_reg, NULL,
    1, 16, 16, 1, 16, 8,
    NULL, NULL, &sysd_reset,
    NULL, NULL, NULL,
    NULL, 0
    };

/* Special boot command, overrides regular boot */
示例#25
0
t_stat todr_resync (void);
t_stat fl_wr_txdb (int32 data);
t_bool fl_test_xfr (UNIT *uptr, t_bool wr);
void fl_protocol_error (void);

/* TTI data structures

   tti_dev      TTI device descriptor
   tti_unit     TTI unit descriptor
   tti_reg      TTI register list
*/

UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };

REG tti_reg[] = {
    { HRDATA (RXDB, tti_buf, 16) },
    { HRDATA (RXCS, tti_csr, 16) },
    { FLDATA (INT, tti_int, 0) },
    { FLDATA (DONE, tti_csr, CSR_V_DONE) },
    { FLDATA (IE, tti_csr, CSR_V_IE) },
    { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
    { NULL }
    };

MTAB tti_mod[] = {
    { TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
    { TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
    { 0 }
    };
示例#26
0
文件: isbc202.c 项目: pkoning2/simh
uint8 isbc202(t_bool io, uint8 data, uint8 devnum);    /* isbc202*/
t_stat isbc202_reset(DEVICE *dptr, uint16 base, uint8 devnum);

/* external function prototypes */

extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint16 port, uint8 devnum);

/* globals */

UNIT isbc202_unit[] = {
    { UDATA (0, 0, 0) },                /* isbc202*/
};

REG isbc202_reg[] = {
    { HRDATA (CONTROL0, isbc202_unit[0].u3, 8) }, /* isbc202 */
    { NULL }
};

DEBTAB isbc202_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "XACK", DEBUG_xack },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }
};

/* address width is set to 16 bits to use devices in 8086/8088 implementations */
示例#27
0
static UNIT if3_unit[] = {
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE | UNIT_IF3_CONNECT, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) },
    { UDATA (&if3_svc, UNIT_FIX | UNIT_DISABLE | UNIT_ROABLE, 0) }
};

static uint8 if3_user = 0;
static uint8 if3_board = 0;
static uint8 if3_rimr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_timr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_risr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };
static uint8 if3_tisr[IF3_MAX_BOARDS] = { 0, 0, 0, 0 };

static REG if3_reg[] = {
    { HRDATA (USER,     if3_user,       3), },
    { HRDATA (BOARD,    if3_board,      2), },
    { BRDATA (RIMR,     &if3_rimr[0],   16, 8, 4), },
    { BRDATA (RISR,     &if3_risr[0],   16, 8, 4), },
    { BRDATA (TIMR,     &if3_timr[0],   16, 8, 4), },
    { BRDATA (TISR,     &if3_tisr[0],   16, 8, 4), },
    { NULL }
};

static MTAB if3_mod[] = {
    { MTAB_XTD|MTAB_VDV,    0,               "IOBASE",   "IOBASE",        &set_iobase, &show_iobase, NULL },
    { UNIT_IF3_CONNECT,     UNIT_IF3_CONNECT,"INSTALLED",  "INSTALLED",   &set_if3_connect, NULL, NULL },
    { UNIT_IF3_CONNECT,     0,               "UNINSTALLED","UNINSTALLED", &set_if3_connect, NULL, NULL },
    { 0 }
};
示例#28
0
extern int32 PutMem(int32 addr, int32 data);

/* Card reader data structures

   cdr_dev      CDR descriptor
   cdr_unit     CDR unit descriptor
   cdr_reg      CDR register list
*/

UNIT cdr_unit = { UDATA (&cdr_svc, UNIT_SEQ+UNIT_ATTABLE, 0), 100 };

REG cdr_reg[] = {
    { FLDATA (LAST, lastcard, 0) },
    { FLDATA (ERR, carderr, 0) },
    { FLDATA (NOTRDY, notready, 0) },
    { HRDATA (DAR, DAR, 16) },
    { HRDATA (LCR, LCR, 16) },
    { FLDATA (EBCDIC, cdr_ebcdic, 0) },
    { FLDATA (S2, s2sel, 0) },
    { DRDATA (POS, cdr_unit.pos, T_ADDR_W), PV_LEFT },
    { DRDATA (TIME, cdr_unit.wait, 24), PV_LEFT },
    { BRDATA (BUF, rbuf, 8, 8, CDR_WIDTH) },
    { NULL }
};

DEVICE cdr_dev = {
    "CDR", &cdr_unit, cdr_reg, NULL,
    1, 10, 31, 1, 8, 7,
    NULL, NULL, &cd_reset,
    &cdr_boot, &cdr_attach, NULL
};
示例#29
0
文件: i8272.c 项目: tjmerritt/simh
int32 i8272_devnum = 0;             //initially, no 8272 instances
uint16 i8272_port[4];               //base port assigned to each 8272 instance

/* i8272 Standard I/O Data Structures */
/* up to 4 i8282 devices */

UNIT i8272_unit[4] = { 
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT },
    { UDATA (&i8272_svc, 0, 0), KBD_POLL_WAIT }
};

REG i8272_reg[4] = {
    { HRDATA (DATA, i8272_unit[0].buf, 8) },
    { HRDATA (STAT, i8272_unit[0].u3, 8) },
    { HRDATA (MODE, i8272_unit[0].u4, 8) },
    { HRDATA (CMD, i8272_unit[0].u5, 8) }
};

DEBTAB i8272_debug[] = {
    { "ALL", DEBUG_all },
    { "FLOW", DEBUG_flow },
    { "READ", DEBUG_read },
    { "WRITE", DEBUG_write },
    { "XACK", DEBUG_xack },
    { "LEV1", DEBUG_level1 },
    { "LEV2", DEBUG_level2 },
    { NULL }
};
示例#30
0
文件: id_mt.c 项目: ST3ALth/simh
   mt_unit      MT unit list
   mt_reg       MT register list
   mt_mod       MT modifier list
*/

DIB mt_dib = { d_MT, 0, v_MT, mt_tplte, &mt, NULL };

UNIT mt_unit[] = {
    { UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
    { UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
    { UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) },
    { UDATA (&mt_svc, UNIT_ATTABLE + UNIT_ROABLE + UNIT_DISABLE, 0) }
    };

REG mt_reg[] = {
    { HRDATA (STA, mt_sta, 8) },
    { HRDATA (BUF, mt_db, 8) },
    { BRDATA (DBUF, mtxb, 16, 8, MT_MAXFR) },
    { HRDATA (DBPTR, mt_bptr, 16) },
    { HRDATA (DBLNT, mt_blnt, 17), REG_RO },
    { FLDATA (XFR, mt_xfr, 0) },
    { GRDATA (IREQ, int_req[l_MT], 16, MT_NUMDR, i_MT) },
    { GRDATA (IENB, int_enb[l_MT], 16, MT_NUMDR, i_MT) },
    { BRDATA (IARM, mt_arm, 16, 1, MT_NUMDR) },
    { FLDATA (STOP_IOE, mt_stopioe, 0) },
    { DRDATA (WTIME, mt_wtime, 24), PV_LEFT + REG_NZ },
    { DRDATA (RTIME, mt_rtime, 24), PV_LEFT + REG_NZ },
    { URDATA (UST, mt_unit[0].UST, 16, 8, 0, MT_NUMDR, 0) },
    { URDATA (CMD, mt_unit[0].UCMD, 16, 8, 0, MT_NUMDR, 0) },
    { URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
              MT_NUMDR, PV_LEFT | REG_RO) },