/**
* hsi_softreset - Force a SW RESET of HSI (core + DMA)
*
* @hsi_ctrl - reference to the hsi controller to be reset.
*
*/
int hsi_softreset(struct hsi_dev *hsi_ctrl)
{
unsigned int ind = 0;
unsigned int port;
void __iomem *base = hsi_ctrl->base;
u32 status;
/* HSI-C1BUG00088: i696 : HSI: Issue with SW reset
* No recovery from SW reset under specific circumstances
* If a SW RESET is done while some HSI errors are still not
* acknowledged, the HSR FSM is stucked. */
if (is_hsi_errata(hsi_ctrl, HSI_ERRATUM_i696_SW_RESET_FSM_STUCK)) {
for (port = 1; port <= hsi_ctrl->max_p; port++) {
hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base,
HSI_HSR_MODE_REG(port));
hsi_outl(HSI_HSR_ERROR_ALL, base,
HSI_HSR_ERRORACK_REG(port));
}
}
/* Reseting HSI Block */
hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG);
do {
status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG);
ind++;
} while ((!(status & HSI_RESETDONE)) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within"
" %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
} else if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
ind = 0;
/* Reseting DMA Engine */
hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG);
do {
status = hsi_inl(base, HSI_GDD_GRST_REG);
ind++;
} while ((status & HSI_GDD_GRST_SWRESET) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete"
" within %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
}
if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
return 0;
}
/**
* hsi_softreset - Force a SW RESET of HSI (core + DMA)
*
* @hsi_ctrl - reference to the hsi controller to be reset.
*
*/
int hsi_softreset(struct hsi_dev *hsi_ctrl)
{
unsigned int ind = 0;
unsigned int port;
void __iomem *base = hsi_ctrl->base;
u32 status;
/* SW WA for HSI-C1BUG00088 OMAP4430 HSI : No recovery from SW reset */
/* under specific circumstances */
for (port = 1; port <= hsi_ctrl->max_p; port++) {
hsi_outl_and(HSI_HSR_MODE_MODE_VAL_SLEEP, base,
HSI_HSR_MODE_REG(port));
hsi_outl(HSI_HSR_ERROR_ALL, base, HSI_HSR_ERRORACK_REG(port));
}
/* Reseting HSI Block */
hsi_outl_or(HSI_SOFTRESET, base, HSI_SYS_SYSCONFIG_REG);
do {
status = hsi_inl(base, HSI_SYS_SYSSTATUS_REG);
ind++;
} while ((!(status & HSI_RESETDONE)) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI SW_RESET failed to complete within"
" %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
} else if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
ind = 0;
/* Reseting DMA Engine */
hsi_outl_or(HSI_GDD_GRST_SWRESET, base, HSI_GDD_GRST_REG);
do {
status = hsi_inl(base, HSI_GDD_GRST_REG);
ind++;
} while ((status & HSI_GDD_GRST_SWRESET) &&
(ind < HSI_RESETDONE_MAX_RETRIES));
if (ind >= HSI_RESETDONE_MAX_RETRIES) {
dev_err(hsi_ctrl->dev, "HSI DMA SW_RESET failed to complete"
" within %d retries.\n", HSI_RESETDONE_MAX_RETRIES);
return -EIO;
}
if (ind > HSI_RESETDONE_NORMAL_RETRIES) {
dev_warn(hsi_ctrl->dev, "HSI DMA SW_RESET abnormally long:"
" %d retries to complete.\n", ind);
}
return 0;
}
/**
* hsi_driver_int_proc - check all channels / ports for interrupts events
* @hsi_ctrl - HSI controler data
* @status_offset: interrupt status register offset
* @enable_offset: interrupt enable regiser offset
* @start: interrupt index to start on
* @stop: interrupt index to stop on
*
* This function calls the related processing functions and triggered events
*/
static void hsi_driver_int_proc(struct hsi_port *pport,
unsigned long status_offset, unsigned long enable_offset,
unsigned int start, unsigned int stop)
{
struct hsi_dev *hsi_ctrl = pport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int port = pport->port_number;
unsigned int channel;
u32 status_reg;
u32 hsr_err_reg;
u32 channels_served = 0;
status_reg = hsi_inl(base, status_offset);
status_reg &= hsi_inl(base, enable_offset);
for (channel = start; channel < stop; channel++) {
if (status_reg & HSI_HST_DATAACCEPT(channel)) {
do_channel_tx(&pport->hsi_channel[channel]);
channels_served |= HSI_HST_DATAACCEPT(channel);
}
if (status_reg & HSI_HSR_DATAAVAILABLE(channel)) {
do_channel_rx(&pport->hsi_channel[channel]);
channels_served |= HSI_HSR_DATAAVAILABLE(channel);
}
}
if (status_reg & HSI_BREAKDETECTED) {
dev_info(hsi_ctrl->dev, "Hardware BREAK on port %d\n", port);
hsi_outl(0, base, HSI_HSR_BREAK_REG(port));
hsi_port_event_handler(pport, HSI_EVENT_BREAK_DETECTED, NULL);
channels_served |= HSI_BREAKDETECTED;
}
if (status_reg & HSI_ERROROCCURED) {
hsr_err_reg = hsi_inl(base, HSI_HSR_ERROR_REG(port));
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x\n",
port, hsr_err_reg);
hsi_outl(hsr_err_reg, base, HSI_HSR_ERRORACK_REG(port));
if (hsr_err_reg) /* ignore spurious errors */
hsi_port_event_handler(pport, HSI_EVENT_ERROR, NULL);
else
dev_dbg(hsi_ctrl->dev, "Spurious HSI error!\n");
channels_served |= HSI_ERROROCCURED;
}
hsi_outl(channels_served, base, status_offset);
}
/**
* hsi_driver_int_proc - check all channels / ports for interrupts events
* @hsi_ctrl - HSI controler data
* @status_offset: interrupt status register offset
* @enable_offset: interrupt enable regiser offset
* @start: interrupt index to start on
* @stop: interrupt index to stop on
*
* returns the bitmap of processed events
*
* This function calls the related processing functions and triggered events.
* Events are cleared after corresponding function has been called.
*/
static u32 hsi_driver_int_proc(struct hsi_port *pport,
unsigned long status_offset,
unsigned long enable_offset, unsigned int start,
unsigned int stop,
bool cawake_double_int)
{
struct hsi_dev *hsi_ctrl = pport->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int port = pport->port_number;
unsigned int channel;
u32 status_reg;
u32 hsr_err_reg;
u32 channels_served = 0;
/* Get events status */
status_reg = hsi_inl(base, status_offset);
status_reg &= hsi_inl(base, enable_offset);
/* Check if we need to process an additional CAWAKE interrupt */
if (cawake_double_int)
status_reg |= HSI_CAWAKEDETECTED;
if (pport->cawake_off_event) {
dev_dbg(hsi_ctrl->dev, "CAWAKE detected from OFF mode.\n");
} else if (!status_reg) {
dev_dbg(hsi_ctrl->dev, "Channels [%d,%d] : no event, exit.\n",
start, stop);
return 0;
} else {
dev_dbg(hsi_ctrl->dev, "Channels [%d,%d] : Events 0x%08x\n",
start, stop, status_reg);
}
if (status_reg & HSI_BREAKDETECTED) {
dev_info(hsi_ctrl->dev, "Hardware BREAK on port %d\n", port);
spin_unlock(&hsi_ctrl->lock);
hsi_port_event_handler(pport, HSI_EVENT_BREAK_DETECTED, NULL);
spin_lock(&hsi_ctrl->lock);
channels_served |= HSI_BREAKDETECTED;
}
if (status_reg & HSI_ERROROCCURED) {
hsr_err_reg = hsi_inl(base, HSI_HSR_ERROR_REG(port));
if (hsr_err_reg & HSI_HSR_ERROR_SIG)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Signal Error");
if (hsr_err_reg & HSI_HSR_ERROR_FTE)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Frame Timeout Error");
if (hsr_err_reg & HSI_HSR_ERROR_TBE)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "Tailing Bit Error");
if (hsr_err_reg & HSI_HSR_ERROR_RME)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "RX Mapping Error");
if (hsr_err_reg & HSI_HSR_ERROR_TME)
dev_err(hsi_ctrl->dev, "HSI ERROR Port %d: 0x%x: %s\n",
port, hsr_err_reg, "TX Mapping Error");
/* Clear error event bit */
hsi_outl(hsr_err_reg, base, HSI_HSR_ERRORACK_REG(port));
if (hsr_err_reg) { /* ignore spurious errors */
spin_unlock(&hsi_ctrl->lock);
hsi_port_event_handler(pport, HSI_EVENT_ERROR, NULL);
spin_lock(&hsi_ctrl->lock);
} else
dev_dbg(hsi_ctrl->dev, "Spurious HSI error!\n");
channels_served |= HSI_ERROROCCURED;
}
for (channel = start; channel <= stop; channel++) {
if (status_reg & HSI_HST_DATAACCEPT(channel)) {
hsi_do_channel_tx(&pport->hsi_channel[channel]);
channels_served |= HSI_HST_DATAACCEPT(channel);
}
if (status_reg & HSI_HSR_DATAAVAILABLE(channel)) {
hsi_do_channel_rx(&pport->hsi_channel[channel]);
channels_served |= HSI_HSR_DATAAVAILABLE(channel);
}
if (status_reg & HSI_HSR_DATAOVERRUN(channel)) {
/*HSI_TODO : Data overrun handling*/
dev_err(hsi_ctrl->dev,
"Data overrun in real time mode !\n");
}
}
/* CAWAKE falling or rising edge detected */
if ((status_reg & HSI_CAWAKEDETECTED) || pport->cawake_off_event) {
if (hsi_do_cawake_process(pport) == -EAGAIN)
goto proc_done;
channels_served |= HSI_CAWAKEDETECTED;
pport->cawake_off_event = false;
}
proc_done:
/* Reset status bits */
hsi_outl(channels_served, base, status_offset);
return channels_served;
}
static int hsi_debug_port_show(struct seq_file *m, void *p)
{
struct hsi_port *hsi_port = m->private;
struct hsi_dev *hsi_ctrl = hsi_port->hsi_controller;
void __iomem *base = hsi_ctrl->base;
unsigned int port = hsi_port->port_number;
int ch, fifo;
long buff_offset;
struct platform_device *pdev = to_platform_device(hsi_ctrl->dev);
hsi_clocks_enable(hsi_ctrl->dev, __func__);
if (hsi_port->cawake_gpio >= 0)
seq_printf(m, "CAWAKE\t\t: %d\n", hsi_get_cawake(hsi_port));
seq_printf(m, "WAKE\t\t: 0x%08x\n",
hsi_inl(base, HSI_SYS_WAKE_REG(port)));
seq_printf(m, "MPU_ENABLE_IRQ%d\t: 0x%08x\n", hsi_port->n_irq,
hsi_inl(base,
HSI_SYS_MPU_ENABLE_REG(port, hsi_port->n_irq)));
seq_printf(m, "MPU_STATUS_IRQ%d\t: 0x%08x\n", hsi_port->n_irq,
hsi_inl(base,
HSI_SYS_MPU_STATUS_REG(port, hsi_port->n_irq)));
if (hsi_driver_device_is_hsi(pdev)) {
seq_printf(m, "MPU_U_ENABLE_IRQ%d\t: 0x%08x\n",
hsi_port->n_irq,
hsi_inl(base, HSI_SYS_MPU_U_ENABLE_REG(port,
hsi_port->n_irq)));
seq_printf(m, "MPU_U_STATUS_IRQ%d\t: 0x%08x\n", hsi_port->n_irq,
hsi_inl(base,
HSI_SYS_MPU_U_STATUS_REG(port,
hsi_port->n_irq)));
}
/* HST */
seq_printf(m, "\nHST\n===\n");
seq_printf(m, "MODE\t\t: 0x%08x\n",
hsi_inl(base, HSI_HST_MODE_REG(port)));
seq_printf(m, "FRAMESIZE\t: 0x%08x\n",
hsi_inl(base, HSI_HST_FRAMESIZE_REG(port)));
seq_printf(m, "DIVISOR\t\t: 0x%08x\n",
hsi_inl(base, HSI_HST_DIVISOR_REG(port)));
seq_printf(m, "CHANNELS\t: 0x%08x\n",
hsi_inl(base, HSI_HST_CHANNELS_REG(port)));
seq_printf(m, "ARBMODE\t\t: 0x%08x\n",
hsi_inl(base, HSI_HST_ARBMODE_REG(port)));
seq_printf(m, "TXSTATE\t\t: 0x%08x\n",
hsi_inl(base, HSI_HST_TXSTATE_REG(port)));
if (hsi_driver_device_is_hsi(pdev)) {
seq_printf(m, "BUFSTATE P1\t: 0x%08x\n",
hsi_inl(base, HSI_HST_BUFSTATE_REG(1)));
seq_printf(m, "BUFSTATE P2\t: 0x%08x\n",
hsi_inl(base, HSI_HST_BUFSTATE_REG(2)));
} else {
seq_printf(m, "BUFSTATE\t: 0x%08x\n",
hsi_inl(base, HSI_HST_BUFSTATE_REG(port)));
}
seq_printf(m, "BREAK\t\t: 0x%08x\n",
hsi_inl(base, HSI_HST_BREAK_REG(port)));
for (ch = 0; ch < 8; ch++) {
buff_offset = hsi_hst_buffer_reg(hsi_ctrl, port, ch);
if (buff_offset >= 0)
seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch,
hsi_inl(base, buff_offset));
}
if (hsi_driver_device_is_hsi(pdev)) {
for (fifo = 0; fifo < HSI_HST_FIFO_COUNT; fifo++) {
seq_printf(m, "FIFO MAPPING%d\t: 0x%08x\n", fifo,
hsi_inl(base,
HSI_HST_MAPPING_FIFO_REG(fifo)));
}
}
/* HSR */
seq_printf(m, "\nHSR\n===\n");
seq_printf(m, "MODE\t\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_MODE_REG(port)));
seq_printf(m, "FRAMESIZE\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_FRAMESIZE_REG(port)));
seq_printf(m, "CHANNELS\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_CHANNELS_REG(port)));
seq_printf(m, "COUNTERS\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_COUNTERS_REG(port)));
seq_printf(m, "RXSTATE\t\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_RXSTATE_REG(port)));
if (hsi_driver_device_is_hsi(pdev)) {
seq_printf(m, "BUFSTATE P1\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_BUFSTATE_REG(1)));
seq_printf(m, "BUFSTATE P2\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_BUFSTATE_REG(2)));
} else {
seq_printf(m, "BUFSTATE\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_BUFSTATE_REG(port)));
}
seq_printf(m, "BREAK\t\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_BREAK_REG(port)));
seq_printf(m, "ERROR\t\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_ERROR_REG(port)));
seq_printf(m, "ERRORACK\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_ERRORACK_REG(port)));
for (ch = 0; ch < 8; ch++) {
buff_offset = hsi_hsr_buffer_reg(hsi_ctrl, port, ch);
if (buff_offset >= 0)
seq_printf(m, "BUFFER_CH%d\t: 0x%08x\n", ch,
hsi_inl(base, buff_offset));
}
if (hsi_driver_device_is_hsi(pdev)) {
for (fifo = 0; fifo < HSI_HSR_FIFO_COUNT; fifo++) {
seq_printf(m, "FIFO MAPPING%d\t: 0x%08x\n", fifo,
hsi_inl(base,
HSI_HSR_MAPPING_FIFO_REG(fifo)));
}
seq_printf(m, "DLL\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_DLL_REG));
seq_printf(m, "DIVISOR\t: 0x%08x\n",
hsi_inl(base, HSI_HSR_DIVISOR_REG(port)));
}
hsi_clocks_disable(hsi_ctrl->dev, __func__);
return 0;
}
