void HAL_clk_AudioCorePowerDomainDisable
(
HAL_clk_PowerDomainDescType *pmPowerDomainDesc
)
{
uint32 nAddr = pmPowerDomainDesc->nGDSCRAddr;
uint32 nVal;
if(nAddr != 0)
{
nVal = inpdw(nAddr);
/*
* Before disabling the GDS, put the core in reset to ensure that any
* bus transactions are gracefully aborted.
*/
HWIO_OUTF(LPASS_AUDIO_CORE_BCR, BLK_ARES, 0x1);
while(HWIO_IN(LPASS_AUDIO_CORE_BCR) &~ HWIO_LPASS_AUDIO_CORE_BCR_BLK_ARES_BMSK);
/*
* Set the SW PD collapse bit
*/
nVal |= HAL_CLK_GDSCR_SW_COLLAPSE_FMSK;
outpdw(nAddr, nVal);
}
} /* HAL_clk_AudioCorePowerDomainDisable */
void HAL_clk_AudioCorePowerDomainEnable
(
HAL_clk_PowerDomainDescType *pmPowerDomainDesc
)
{
uint32 nAddr,nVal;
nAddr = pmPowerDomainDesc->nGDSCRAddr;
/*
* Sanity check
*/
if(nAddr != 0)
{
nVal = inpdw(nAddr);
/*
* Clear the SW PD collapse bit
*/
nVal &= ~HAL_CLK_GDSCR_SW_COLLAPSE_FMSK;
outpdw(nAddr, nVal);
/*
* Wait for PD ON
*/
while(!(inpdw(nAddr) & HAL_CLK_GDSCR_PWR_ON_FMSK));
/*
* Ensure the reset is cleared.
*/
HWIO_OUTF(LPASS_AUDIO_CORE_BCR, BLK_ARES, 0x0);
HAL_clk_BusyWait(2);
}
} /* HAL_clk_AudioCorePowerDomainEnable */
static void HAL_clk_Q6CoreClkConfig
(
HAL_clk_ClockDescType *pmClockDesc,
HAL_clk_ClockConfigType eConfig
)
{
uint32 nSrcSel;
switch (eConfig)
{
case HAL_CLK_CONFIG_Q6SS_CORE_CLOCK_MUX_SRCA:
nSrcSel = 0x0;
break;
case HAL_CLK_CONFIG_Q6SS_CORE_CLOCK_MUX_SRCB:
nSrcSel = 0x1;
break;
case HAL_CLK_CONFIG_Q6SS_CORE_CLOCK_MUX_SRCC:
nSrcSel = 0x2;
break;
case HAL_CLK_CONFIG_Q6SS_CORE_CLOCK_MUX_SRCD:
nSrcSel = 0x3;
break;
default:
return;
}
HWIO_OUTF(LPASS_QDSP6SS_GFMUX_CTL, CLK_SRC_SEL, nSrcSel);
} /* END HAL_clk_Q6CoreClkConfig */
/*===========================================================================
FUNCTION HSU_PHY_UTILS_SPOOF_DISCONNECT
DESCRIPTION
This function causes the device to disconnect from host,
while USB cable can still be attached.
DEPENDENCIES
None.
RETURN VALUE
TRUE - Operation successful. FALSE - Otherwise.
SIDE EFFECTS
None.
===========================================================================*/
boolean hsu_phy_utils_spoof_disconnect(void)
{
#ifdef FEATURE_HS_USB_INTEGRATED_PHY
#ifndef FEATURE_HS_USB_HAL
const uint32 MAX_SPOOF_DISCONNECT_GUARD_LOOP = 10000;
uint32 loop_itor;
#endif /* FEATURE_HS_USB_HAL */
#endif /* FEATURE_HS_USB_INTEGRATED_PHY */
/* Stop the core */
#ifdef FEATURE_HS_USB_HAL
HAL_hsusb_ClearBits32(0, HAL_HSUSB_USBCMD_ADDR, HAL_HSUSB_USBCMD_RS_BMSK);
#else /* FEATURE_HS_USB_HAL */
HWIO_OUTF(USB_OTG_HS_USBCMD, RS, 0);
#endif /* FEATURE_HS_USB_HAL */
#ifdef FEATURE_HS_USB_INTEGRATED_PHY
/* SW workaround for intg. phy in which clearing the RS bit does not pull down D+
Write function control register:
bits [3,4] (OpMode) = [0,1] (Non-Driving)
bit [6] (SuspendM) = [1] (Normal Power) */
#ifdef FEATURE_HS_USB_HAL
if (HAL_hsusb_WriteUlpiPhy(0, 0, 0x4, 0x48) == HAL_HSUSB_Success)
{
return TRUE;
}
#else /* FEATURE_HS_USB_HAL */
HWIO_OUT(USB_OTG_HS_ULPI_VIEWPORT, 0x60040048);
for (loop_itor = 0 ; loop_itor < MAX_SPOOF_DISCONNECT_GUARD_LOOP
; ++loop_itor)
{
/* Wait until the ULPI running bit is cleared */
if (!(HWIO_INF(USB_OTG_HS_ULPI_VIEWPORT, ULPIRUN)))
{
return TRUE;
}
}
#endif /* FEATURE_HS_USB_HAL */
HSU_MSG_ERROR("hsu_os_bus_spoof_disconnect: couldn't write termselect",
0, 0, 0);
return FALSE;
#else /* !FEATURE_HS_USB_INTEGRATED_PHY */
return TRUE;
#endif /* FEATURE_HS_USB_INTEGRATED_PHY */
} /* hsu_phy_utils_spoof_disconnect */
boolean uClock_DisableClock(uClockIdType eClockId)
{
// if(uClockDriverCtxt.bInitialized == FALSE)
// {
// qurt_mutex_init(&uClockDriverCtxt.Mutex);
// uClockDriverCtxt.bInitialized = TRUE;
// }
if(eClockId < CLOCK_TOTAL_CLOCK_ENUMS)
{
// qurt_mutex_lock(&uClockDriverCtxt.Mutex);
if(uClockDriverCtxt.anClockReferences[eClockId] > 0)
{
uClockDriverCtxt.anClockReferences[eClockId]--;
}
if(uClockDriverCtxt.anClockReferences[eClockId] == 0)
{
switch(eClockId)
{
case CLOCK_GCC_BLSP1_QUP1_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP1_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_QUP2_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP2_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_QUP3_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP3_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_QUP4_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP4_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_QUP5_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP5_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_QUP6_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP6_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP1_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP1_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP2_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP2_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP3_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP3_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP4_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP4_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP5_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP5_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP2_QUP6_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP6_I2C_APPS_CBCR, CLK_ENABLE, 0x0);
break;
case CLOCK_GCC_BLSP1_AHB_CLK:
HWIO_OUTF(GCC_SPARE_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA, 0x0);
break;
case CLOCK_GCC_BLSP2_AHB_CLK:
HWIO_OUTF(GCC_SPARE_CLOCK_BRANCH_ENA_VOTE, BLSP2_AHB_CLK_ENA, 0x0);
break;
default:
break;
}
}
// qurt_mutex_unlock(&uClockDriverCtxt.Mutex);
return(TRUE);
}
return(FALSE);
} /* uClock_DisableClock */
boolean uClock_EnableClock(uClockIdType eClockId)
{
boolean bRetVal = TRUE;
uint32 nTimeout = 150;
// if(uClockDriverCtxt.bInitialized == FALSE)
// {
// qurt_mutex_init(&uClockDriverCtxt.Mutex);
// uClockDriverCtxt.bInitialized = TRUE;
// }
if(eClockId < CLOCK_TOTAL_CLOCK_ENUMS)
{
// qurt_mutex_lock(&uClockDriverCtxt.Mutex);
if(uClockDriverCtxt.anClockReferences[eClockId] == 0)
{
switch(eClockId)
{
case CLOCK_GCC_BLSP1_QUP1_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP1_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_QUP2_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP2_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_QUP3_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP3_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_QUP4_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP4_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_QUP5_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP5_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_QUP6_APPS_CLK:
HWIO_OUTF(GCC_BLSP1_QUP6_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP1_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP1_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP2_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP2_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP3_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP3_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP4_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP4_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP5_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP5_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP2_QUP6_APPS_CLK:
HWIO_OUTF(GCC_BLSP2_QUP6_I2C_APPS_CBCR, CLK_ENABLE, 0x1);
break;
case CLOCK_GCC_BLSP1_AHB_CLK:
HWIO_OUTF(GCC_SPARE_CLOCK_BRANCH_ENA_VOTE, BLSP1_AHB_CLK_ENA, 0x1);
break;
case CLOCK_GCC_BLSP2_AHB_CLK:
HWIO_OUTF(GCC_SPARE_CLOCK_BRANCH_ENA_VOTE, BLSP2_AHB_CLK_ENA, 0x1);
break;
default:
bRetVal = FALSE;
break;
}
while(uClock_IsOn(eClockId) != TRUE)
{
if(nTimeout == 0)
{
break;
}
busywait(2);
nTimeout--;
}
}
/*
* Increase the reference count on this clock.
*/
if(nTimeout != 0)
{
uClockDriverCtxt.anClockReferences[eClockId]++;
bRetVal = TRUE;
}
else
{
bRetVal = FALSE;
}
// qurt_mutex_unlock(&uClockDriverCtxt.Mutex);
return(bRetVal);
}
return(FALSE);
} /* uClock_EnableClock */
void HAL_clk_PlatformInitLPASSMain (void)
{
/*
* Filter out clocks not supported on the current chipset.
*/
HAL_clk_FilterClockDomains(HAL_clk_aLPASSClockDomainDesc);
/*
* Install all clock domains
*/
HAL_clk_InstallClockDomains(HAL_clk_aLPASSClockDomainDesc, LPASS_BASE);
/*
* Install all power domains
*/
HAL_clk_InstallPowerDomains(HAL_clk_aLPASSPowerDomainDesc, LPASS_BASE);
/*
* SW workaround for HW issue that fails to default the sleep and wake POR
* values for LPM to max. Set values to max (0xF) here.
*/
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM0_CBCR, WAKEUP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM0_CBCR, SLEEP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM1_CBCR, WAKEUP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM1_CBCR, SLEEP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM2_CBCR, WAKEUP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM2_CBCR, SLEEP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM3_CBCR, WAKEUP, 0xF);
HWIO_OUTF(LPASS_AUDIO_CORE_LPM_MEM3_CBCR, SLEEP, 0xF);
/*
* Need to modify the AUDIO_CORE_GDSC register defaults to allow enough
* time for the clock to propagate before deasserting the clamp.
*/
HWIO_OUTF(LPASS_AUDIO_CORE_GDSCR, EN_REST_WAIT, 0x2);
HWIO_OUTF(LPASS_AUDIO_CORE_GDSCR, EN_FEW_WAIT, 0x2);
HWIO_OUTF(LPASS_AUDIO_CORE_GDSCR, CLK_DIS_WAIT, 0x2);
} /* END HAL_clk_PlatformInitLPASSMain */
