/**
* \brief This API enables the RX DMA for an endPoint.The API access the CSR
* register of the particular endpoint to set appropriate bits. This API is
* called by the stack to enable DMA when it is requied.
*
* \param usbDevInst:- USB device instance
*
* \param ulEndpoint:- Endpoint Number
*
* \return None.
*
**/
void enableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
{
unsigned int ulRegister;
usbInstance *usbInstance;
usbInstance = &(cppiInfo.usbInst[usbDevInst]);
/*Find out the RX CSR address */
ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
/*Find out the index to usb intance end point array */
ulEndpoint = USB_EP_TO_INDEX(ulEndpoint);
/*Enable the scheduler with number entries */
Cppi41DmaControlScheduler(usbDevInst, ENABLE_CPPIDMA, NUM_OF_SCHEDULER_ENTRIES);
/*Configure the completion queue */
Cppi41DmaConfigRxCompletionQueue(usbDevInst, usbInstance->rxEndPoint[ulEndpoint].channel,
usbInstance->rxEndPoint[ulEndpoint].complettionq);
/* Clear AUTOCLEAR and DMAReqMode */
HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_RX_CLR_AUTO_CLEAR;
/* Set DMAReqEnab */
HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_RX_SET_REQ_ENABLE;
}
////////////////////////////////////////////////////////////////////////////////
//----获取刷卡记录数------------------------------------------------------------
void AddrPoinitInit(RECORDINF* paddrlist)
{
u16 cnt;
u32 addr;
//从页首地址
addr = paddrlist->baseaddr;
cnt = HWREGH(addr);
//记录是0
if( cnt == 0xFFFF )
{
paddrlist->RecordCount = 0;
paddrlist->CountAddrOffset = 0;
return;
}
addr += 2;
//开始查询
for( paddrlist->CountAddrOffset=2; paddrlist->CountAddrOffset<FLASH_PAGE_SPACE; paddrlist->CountAddrOffset+=2)
{
cnt = HWREGH(addr);
//找到最后一个计数值
if( cnt == 0xFFFF )
{
addr -= 2;
paddrlist->RecordCount = HWREGH(addr);
return;
}
addr += 2;
}
paddrlist->RecordCount = cnt; //修改，曾经出现bug，后果很严重
return;
}
/**
* \brief This function configures ECAP to One-shot mode and also
* stop value for this mode.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \param stopVal It is the number of captures allowed to occur before
* Capture register(1-4) are frozen.\n
*
* stopVal can take following macros.\n
*
* ECAP_CAPTURE_EVENT1_STOP - stop after Capture Event 1\n.
* ECAP_CAPTURE_EVENT2_STOP - stop after Capture Event 2\n.
* ECAP_CAPTURE_EVENT3_STOP - stop after Capture Event 3\n.
* ECAP_CAPTURE_EVENT4_STOP - stop after Capture Event 4\n.
*
* \return None.\n
*
* This API is valid only if ECAP is configured to Capture Mode.It has
* no significance when ECAP is configured in APWM mode.
**/
void ECAPOneShotModeConfig(unsigned int baseAdd, unsigned int stopVal)
{
HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_CONT_ONESHT;
HWREGH(baseAdd + ECAP_ECCTL2) &= 0xfffffff9;
HWREGH(baseAdd + ECAP_ECCTL2) |= stopVal;
}
/**
* \brief This function configures Sync-In and Sync-Out.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param syncIn It is the value which determines whether to disable
* syncIn or to enable counter to be loaded from
* CNTPHS register upon a SYNCI signal.\n
*
* syncIn can take following macros.\n
*
* ECAP_SYNC_IN_DISABLE.\n
* ECAP_ENABLE_COUNTER - Enables counter to load from CNTPHS
* register upon SYNCI signal.\n
*
* \param syncOut It is the value which select type of syncOut signal
* (i.e select syncIn event to be the Sync-Out signal,
* select PRD_eq event to be Sync-Out signal).\n
*
*
* syncOut can take following macros.\n
*
* ECAP_SYNC_IN - Select syncIn event to be the Sync-Out signal.\n
* ECAP_PRD_EQ - Select PRD_eq event to be Sync-Out signal.\n
* ECAP_SYNC_OUT_DISABLE - Disable syncOut signal.\n
*
* \return None.
*
**/
void ECAPSyncInOutSelect(unsigned int baseAdd, unsigned int syncIn,
unsigned int syncOut)
{
HWREGH(baseAdd + ECAP_ECCTL2) &= 0xffffffdf;
HWREGH(baseAdd + ECAP_ECCTL2) |= syncIn;
HWREGH(baseAdd + ECAP_ECCTL2) &= 0xffffff3f;
HWREGH(baseAdd + ECAP_ECCTL2) |= syncOut;
}
/**
* \brief This function configures Capture Event polarity.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param capEvt1pol It determines whether Capture Event1 has to be generated
* on rising edge or falling edge of pulse.
*
* \param capEvt2pol It determines whether Capture Event2 has to be generated
* on rising edge or falling edge of pulse.
*
* \param capEvt3pol It determines whether Capture Event3 has to be generated
* on rising edge or falling edge of pulse.
*
* \param capEvt4pol It determines whether Capture Event4 has to be generated
* on rising edge or falling edge of pulse.
*
* 0 - falling edge
* 1 - rising edge
* \return None.
*
**/
void ECAPCapeEvtPolarityConfig(unsigned int baseAdd, unsigned int capEvt1pol,
unsigned int capEvt2pol, unsigned int capEvt3pol,
unsigned int capEvt4pol)
{
HWREGH(baseAdd + ECAP_ECCTL1) |= capEvt1pol << 0;
HWREGH(baseAdd + ECAP_ECCTL1) |= capEvt2pol << 2;
HWREGH(baseAdd + ECAP_ECCTL1) |= capEvt3pol << 4;
HWREGH(baseAdd + ECAP_ECCTL1) |= capEvt4pol << 6;
}
/**
* \brief This function enables reset of the counters upon Capture Events.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param CounterRst1 It determines whether counter has to be reset upon
* Capture Event1.
*
* \param CounterRst2 It determines whether counter has to be reset upon
* Capture Event2.
*
* \param CounterRst3 It determines whether counter has to be reset upon
* Capture Event3.
*
* \param CounterRst4 It determines whether counter has to be reset upon
* Capture Event4.
*
* 0 - Don't reset counter upon capture event.\n
* 1 - Reset upon counter capture event.\n
*
* \return None.
*
**/
void ECAPCaptureEvtCntrRstConfig(unsigned int baseAdd, unsigned int CounterRst1,
unsigned int CounterRst2,unsigned int CounterRst3,
unsigned int CounterRst4)
{
HWREGH(baseAdd + ECAP_ECCTL1) |= CounterRst1 << 1;
HWREGH(baseAdd + ECAP_ECCTL1) |= CounterRst2 << 3;
HWREGH(baseAdd + ECAP_ECCTL1) |= CounterRst3 << 5;
HWREGH(baseAdd + ECAP_ECCTL1) |= CounterRst4 << 7;
}
//*****************************************************************************
//
// CPUTimer_setEmulationMode
//
//*****************************************************************************
void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode)
{
ASSERT(CPUTimer_isBaseValid(base));
// Write to FREE_SOFT bits of register TCR
HWREGH(base + CPUTIMER_O_TCR) =
(HWREGH(base + CPUTIMER_O_TCR) &
~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) |
(uint16_t)mode;
}
/**
* \brief This API can be used to restore the register context of ECAP
*
* \param ecapBase Base address of ECAP instance
* \param pwmssBase Base address of the PWM subsystem
* \param contextPtr Pointer to the structure where ECAP register
* context need to be saved
*
* \return None
*
**/
void EcapContextRestore(unsigned int ecapBase, unsigned int pwmssBase,
ECAPCONTEXT *contextPtr)
{
HWREG(pwmssBase + PWMSS_CLOCK_CONFIG) = contextPtr->pwm0ssclkconfig;
HWREG(ecapBase + ECAP_TSCTR) = contextPtr->tsctr;
HWREGH(ecapBase + ECAP_ECEINT) = contextPtr->eceint;
HWREGH(ecapBase + ECAP_ECCLR) = contextPtr->ecclr;
HWREGH(ecapBase + ECAP_ECCTL2) = contextPtr->ecctl2;
HWREG(ecapBase + ECAP_CAP1) = contextPtr->cap1;
HWREG(ecapBase + ECAP_CAP2) = contextPtr->cap2;
}
/**
* \brief This function configures ecapture module to operate in capture
* mode or in APWM mode.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param modeSelect It is the value which determines whether ecapture
* module to operate in capture mode or in APWM mode.\n
*
* modeSelect can take following macros.
*
* ECAP_CAPTURE_MODE - Capture Mode.\n
* ECAP_APWM_MODE - APWM Mode.\n
*
* \return None.
*
**/
void ECAPOperatingModeSelect(unsigned int baseAdd, unsigned int modeSelect)
{
if(modeSelect)
{
HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM;
}
else
{
HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_CAP_APWM;
}
}
/**
* \brief This API can be used to save the register context of ECAP
*
* \param ecapBase Base address of ECAP instance
* \param pwmssBase Base address of the PWM subsystem
* \param contextPtr Pointer to the structure where ECAP register
* context need to be saved
*
* \return None
*
**/
void EcapContextSave(unsigned int ecapBase, unsigned int pwmssBase,
ECAPCONTEXT *contextPtr)
{
contextPtr->pwm0ssclkconfig = HWREG(pwmssBase + PWMSS_CLOCK_CONFIG);
contextPtr->tsctr = HWREG(ecapBase + ECAP_TSCTR);
contextPtr->eceint = HWREGH(ecapBase + ECAP_ECEINT);
contextPtr->ecclr = HWREGH(ecapBase + ECAP_ECCLR);
contextPtr->ecctl2 = HWREGH(ecapBase + ECAP_ECCTL2);
contextPtr->cap1 = HWREG(ecapBase + ECAP_CAP1);
contextPtr->cap2 = HWREG(ecapBase + ECAP_CAP2);
}
/**
* \brief This function configures counter to stop or free running
* based on its input argument flag.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param flag It is the value which determine counter to be configured
* to stop or free running.\n
*
* flag can take following macros.\n
*
* ECAP_COUNTER_STOP.\n
* ECAP_COUNTER_FREE_RUNNING.\n
*
* \return None.
*
**/
void ECAPCounterControl(unsigned int baseAdd, unsigned int flag)
{
if(flag)
{
HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP;
}
else
{
HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP;
}
}
/**
* \brief This function configures output polarity for APWM output.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param flag It is the value which determines the output polarity
* for APWM output.\n
*
* flag can take following macros.\n
*
* ECAP_APWM_ACTIVE_HIGH.\n
* ECAP_APWM_ACTIVE_LOW.\n
*
* \return None.
*
**/
void ECAPAPWMPolarityConfig(unsigned int baseAdd, unsigned int flag)
{
if(flag)
{
HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_APWMPOL;
}
else
{
HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_APWMPOL;
}
}
/**
* \brief This API enables the TX DMA for an endpont. The API access the CSR
* register of the particular endpoint to set appropriate bits. This API is
* Called by the stack to disable DMA when it is required
*
* \param usbDevInst:- USB device instance
*
* \param ulEndpoint:- Endpoint Number
*
* \return None.
*
**/
void disableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
{
unsigned int ulRegister;
usbInstance *usbInstance;
usbInstance = &(cppiInfo.usbInst[usbDevInst]);
ulRegister = USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint);
while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
/* Clear AUTOSET */
HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_TX_CLR_AUTO_SET;
/* Clear DMAReqEnab & DMAReqMode */
HWREGH(usbInstance->usbBaseAddress + ulRegister)&=CPDMA_TX_CLR_REQ_ENABLE;
}
/**
* \brief This API disables the RX DMA for an endpoint. The API access the CSR
* register of the particular endpoint to set appropriate bits. This API is
* Called by the stack to disable DMA when it is required
*
* \param usbDevInst:- USB device instance
*
* \param ulEndpoint:- Endpoint Number
*
* \return None.
*
**/
void disableCoreRxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
{
unsigned int ulRegister;
usbInstance *usbInstance;
usbInstance = &(cppiInfo.usbInst[usbDevInst]);
/*Find out the CSR offset */
ulRegister = USB_O_RXCSRL1 + EP_OFFSET(ulEndpoint);
/*wait till completion of any previos transaction */
while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x1) == 0x01);
/* Clear DMAReqEnab */
HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_RX_CLR_REQ_ENABLE;
}
void isr_ecap(unsigned int intnum){
MODULE *module = modulelist+intnum;
unsigned short val = HWREGH(module->baseAddr + ECAP_ECFLG);
HWREGH(module->baseAddr + ECAP_ECCLR) = val;
unsigned int val1;
if (val & (1 << 2)) {
val1 = ECAPTimeStampRead(module->baseAddr, ECAP_CAPTURE_EVENT_2);
if (ecaphandlers[module->index] != NULL) {
ecaphandlers[module->index](val1);
}
}
if (val & (1 << 4)) {
val1 = ECAPTimeStampRead(SOC_ECAP_0_REGS, ECAP_CAPTURE_EVENT_2);
if (ecaphandlers[module->index] != NULL) {
ecaphandlers[module->index](val1);
}
}
}
/**
* \brief This API enables the TX DMA for an endpoint. The API access the CSR
* register of the particular endpoint to set appropriate bits. This API is
* called by the stack to enable DMA when it is requied.
*
* \param usbDevInst:- USB device instance
*
* \param ulEndpoint:- Endpoint Number
*
* \return None.
*
**/
void enableCoreTxDMA(unsigned short usbDevInst, unsigned int ulEndpoint)
{
unsigned int ulRegister;
usbInstance *usbInstance;
usbInstance = &(cppiInfo.usbInst[usbDevInst]);
/*Find out the TX CRS address */
ulRegister = USB_O_TXCSRL1 + EP_OFFSET(ulEndpoint);
/*Wait till completion of any previous transaction */
while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
/* Clear Autoset */
HWREGH(usbInstance->usbBaseAddress + ulRegister)&= CPDMA_TX_CLR_AUTO_SET;
/* Set DMAReqEnab & DMAReqMode */
HWREGH(usbInstance->usbBaseAddress + ulRegister)|=CPDMA_TX_SET_REQ_ENABLE;
}
unsigned int dmaTxCompletion(unsigned short usbDevInst, unsigned int ulEndpoint )
{
hostPacketDesc *completed_bd;
unsigned int ulRegister;
unsigned int state;
unsigned int packetid;
usbInstance *usbInstance;
usbInstance = &(cppiInfo.usbInst[usbDevInst]);
ulRegister = USB_O_TXCSRL1 + EP_OFFSET( ulEndpoint);
ulEndpoint = USB_EP_TO_INDEX(ulEndpoint);
/*read the compltetion queue */
completed_bd = (hostPacketDesc *)Cppi41DmaReadCompletionQueue(usbDevInst, usbInstance
->txEndPoint[ulEndpoint].complettionq);
/*Get the packet ID to update the DMA status */
packetid = completed_bd->packetId;
if(packetid == EOP)
state = DMA_TX_COMPLETED;
else
state = DMA_TX_IN_PROGRESS;
/*wait till Tx completion */
if(state == DMA_TX_COMPLETED)
while ((HWREGH(usbInstance->usbBaseAddress + ulRegister) & 0x2) == 0x02);
CacheDataInvalidateBuff((unsigned int)completed_bd->buffAdd, sizeof(completed_bd->buffAdd));
cppiDmaFreenBuffer((unsigned int *)completed_bd->buffAdd);
completed_bd->buffAdd = 0;
/*put the free buffer */
putFreeBd(completed_bd);
return state;
}
/**
* \brief This function extracts the firmware version from IPC message register
*
* \param None
*
* \return CM3 firmware version
*/
unsigned short readCM3FWVersion(void)
{
return (HWREGH(SOC_CONTROL_REGS + CONTROL_IPC_MSG_REG(2)));
}
//*****************************************************************************
//
//! Handles the ADC interrupt for the touch screen.
//!
//! This function is called when the ADC sequence that samples the touch screen
//! has completed its acquisition. The touch screen state machine is advanced
//! and the acquired ADC sample is processed appropriately.
//!
//! It is the responsibility of the application using the touch screen driver
//! to ensure that this function is installed in the interrupt vector table for
//! the ADC3 interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
TouchScreenIntHandler(void)
{
//
// Clear the ADC sample sequence interrupt.
//
HWREG(ADC0_BASE + ADC_O_ISC) = 1 << 3;
//
// Determine what to do based on the current state of the state machine.
//
switch(g_ulTSState)
{
//
// The new sample is an X axis sample that should be discarded.
//
case TS_STATE_SKIP_X:
{
//
// Read and throw away the ADC sample.
//
HWREG(ADC0_BASE + ADC_O_SSFIFO3);
//
// Set the analog mode select for the YP pin.
//
HWREG(TS_P_BASE + GPIO_O_AMSEL) =
HWREG(TS_P_BASE + GPIO_O_AMSEL) | TS_YP_PIN;
//
// Configure the Y axis touch layer pins as inputs.
//
HWREG(TS_P_BASE + GPIO_O_DIR) =
HWREG(TS_P_BASE + GPIO_O_DIR) & ~TS_YP_PIN;
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
HWREGB(LCD_CONTROL_SET_REG) = LCD_CONTROL_YN;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
HWREGH(LCD_FPGA_CONTROL_SET_REG) = LCD_CONTROL_YN;
}
else
{
//
// Default case with no daughter, SDRAM board or any other
// daughter which doesn't mess with the touchscreen interface.
//
HWREG(TS_N_BASE + GPIO_O_DIR) =
HWREG(TS_N_BASE + GPIO_O_DIR) & ~TS_YN_PIN;
}
//
// The next sample will be a valid X axis sample.
//
g_ulTSState = TS_STATE_READ_X;
//
// This state has been handled.
//
break;
}
//
// The new sample is an X axis sample that should be processed.
//
case TS_STATE_READ_X:
{
//
// Read the raw ADC sample.
//
g_sTouchX = HWREG(ADC0_BASE + ADC_O_SSFIFO3);
//
// Clear the analog mode select for the YP pin.
//
HWREG(TS_P_BASE + GPIO_O_AMSEL) =
HWREG(TS_P_BASE + GPIO_O_AMSEL) & ~TS_YP_PIN;
//
// Configure the X and Y axis touch layers as outputs.
//
HWREG(TS_P_BASE + GPIO_O_DIR) =
HWREG(TS_P_BASE + GPIO_O_DIR) | TS_XP_PIN | TS_YP_PIN;
if((g_eDaughterType != DAUGHTER_SRAM_FLASH) &&
(g_eDaughterType != DAUGHTER_FPGA))
{
HWREG(TS_N_BASE + GPIO_O_DIR) =
HWREG(TS_N_BASE + GPIO_O_DIR) | TS_XN_PIN | TS_YN_PIN;
}
//
// Drive the positive side of the Y axis touch layer with VDD and
// the negative side with GND. Also, drive both sides of the X
// axis layer with GND to discharge any residual voltage (so that
// a no-touch condition can be properly detected).
//
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
HWREGB(LCD_CONTROL_CLR_REG) = LCD_CONTROL_XN | LCD_CONTROL_YN;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
HWREGH(LCD_FPGA_CONTROL_CLR_REG) = (LCD_CONTROL_XN |
LCD_CONTROL_YN);
}
else
{
//
// Default case - any daughter which doesn't muck with the
// touchscreen signals.
//
HWREG(TS_N_BASE + GPIO_O_DATA +
((TS_XN_PIN | TS_YN_PIN) << 2)) = 0;
}
HWREG(TS_P_BASE + GPIO_O_DATA + ((TS_XP_PIN | TS_YP_PIN) << 2)) =
TS_YP_PIN;
//
// Configure the sample sequence to capture the X axis value.
//
HWREG(ADC0_BASE + ADC_O_SSMUX3) = ADC_CTL_CH_XP;
//
// The next sample will be an invalid Y axis sample.
//
g_ulTSState = TS_STATE_SKIP_Y;
//
// This state has been handled.
//
break;
}
//
// The new sample is a Y axis sample that should be discarded.
//
case TS_STATE_SKIP_Y:
{
//
// Read and throw away the ADC sample.
//
HWREG(ADC0_BASE + ADC_O_SSFIFO3);
//
// Set the analog mode select for the XP pin.
//
HWREG(TS_P_BASE + GPIO_O_AMSEL) =
HWREG(TS_P_BASE + GPIO_O_AMSEL) | TS_XP_PIN;
//
// Configure the X axis touch layer pins as inputs.
//
HWREG(TS_P_BASE + GPIO_O_DIR) =
HWREG(TS_P_BASE + GPIO_O_DIR) & ~TS_XP_PIN;
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
HWREGB(LCD_CONTROL_SET_REG) = LCD_CONTROL_XN;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
HWREGH(LCD_FPGA_CONTROL_SET_REG) = LCD_CONTROL_XN;
}
else
{
//
// Default case - any daughter which doesn't muck with the
// touchscreen signals.
//
HWREG(TS_N_BASE + GPIO_O_DIR) =
HWREG(TS_N_BASE + GPIO_O_DIR) & ~TS_XN_PIN;
}
//
// The next sample will be a valid Y axis sample.
//
g_ulTSState = TS_STATE_READ_Y;
//
// This state has been handled.
//
break;
}
//
// The new sample is a Y axis sample that should be processed.
//
case TS_STATE_READ_Y:
{
//
// Read the raw ADC sample.
//
g_sTouchY = HWREG(ADC0_BASE + ADC_O_SSFIFO3);
//
// The next configuration is the same as the initial configuration.
// Therefore, fall through into the initialization state to avoid
// duplicating the code.
//
}
//
// The state machine is in its initial state
//
case TS_STATE_INIT:
{
//
// Clear the analog mode select for the XP pin.
//
HWREG(TS_P_BASE + GPIO_O_AMSEL) =
HWREG(TS_P_BASE + GPIO_O_AMSEL) & ~TS_XP_PIN;
//
// Configure the X and Y axis touch layers as outputs.
//
HWREG(TS_P_BASE + GPIO_O_DIR) =
HWREG(TS_P_BASE + GPIO_O_DIR) | TS_XP_PIN | TS_YP_PIN;
if((g_eDaughterType != DAUGHTER_SRAM_FLASH) &&
(g_eDaughterType != DAUGHTER_FPGA))
{
HWREG(TS_N_BASE + GPIO_O_DIR) =
HWREG(TS_N_BASE + GPIO_O_DIR) | TS_XN_PIN | TS_YN_PIN;
}
//
// Drive one side of the X axis touch layer with VDD and the other
// with GND. Also, drive both sides of the Y axis layer with GND
// to discharge any residual voltage (so that a no-touch condition
// can be properly detected).
//
HWREG(TS_P_BASE + GPIO_O_DATA + ((TS_XP_PIN | TS_YP_PIN) << 2)) =
TS_XP_PIN;
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
HWREGB(LCD_CONTROL_CLR_REG) = LCD_CONTROL_XN | LCD_CONTROL_YN;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
HWREGH(LCD_FPGA_CONTROL_CLR_REG) = (LCD_CONTROL_XN |
LCD_CONTROL_YN);
}
else
{
//
// Default case - any daughter which does not muck with the
// touchscreen signals.
//
HWREG(TS_N_BASE + GPIO_O_DATA +
((TS_XN_PIN | TS_YN_PIN) << 2)) = 0;
}
//
// Configure the sample sequence to capture the Y axis value.
//
HWREG(ADC0_BASE + ADC_O_SSMUX3) = ADC_CTL_CH_YP;
//
// If this is the valid Y sample state, then there is a new X/Y
// sample pair. In that case, run the touch screen debouncer.
//
if(g_ulTSState == TS_STATE_READ_Y)
{
TouchScreenDebouncer();
}
//
// The next sample will be an invalid X axis sample.
//
g_ulTSState = TS_STATE_SKIP_X;
//
// This state has been handled.
//
break;
}
}
}
/**
* \brief This function configures prescale value.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param prescale It is the value which is used to prescale the incoming
* input.
*
* prescale can take any integer value between 0 and 62
*
* \return None.
*
**/
void ECAPPrescaleConfig(unsigned int baseAdd, unsigned int prescale)
{
HWREGH(baseAdd + ECAP_ECCTL1) &= 0xffffc1ff;
HWREGH(baseAdd + ECAP_ECCTL1) |= (prescale << ECAP_ECCTL1_PRESCALE_SHIFT);
}
/**
* \brief This function configures ECAP to One-Short Re-arming.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \return None.\n
*
* When this API is invoked following things happen.\n
*
* 1. Resets Mod4 counter to zero.\n
* 2. Un-freezes the Mod4 counter.\n
* 3. Enables capture register loads.\n
*
**/
void ECAPOneShotREARM(unsigned int baseAdd)
{
HWREGH(baseAdd + ECAP_ECCTL2) |= ECAP_ECCTL2_RE_ARM;
}
/**
* \brief This function disables capture loading
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \return None.
*
**/
void ECAPCaptureLoadingDisable(unsigned int baseAdd)
{
HWREGH(baseAdd + ECAP_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN;
}
/**
* \brief This function enables capture loading.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \return None.
*
**/
void ECAPCaptureLoadingEnable(unsigned int baseAdd)
{
HWREGH(baseAdd + ECAP_ECCTL1) |= ECAP_ECCTL1_CAPLDEN;
}
/**
* \brief This function clears of the status specified interrups
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param flag It is the value which specifies the status of interrupts
* to be cleared.\n
*
* flag can take following macros.
*
* ECAP_CEVT1_INT - Status of Capture Event 1 interrupt.\n
* ECAP_CEVT2_INT - Status of Capture Event 2 interrupt.\n
* ECAP_CEVT3_INT - Status of Capture Event 3 interrupt.\n
* ECAP_CEVT4_INT - Status of Capture Event 4 interrupt.\n
* ECAP_CNTOVF_INT - Status of Counter Overflow interrupt.\n
* ECAP_PRDEQ_INT - Status of Period equal interrupt.\n
* ECAP_CMPEQ_INT - Status of Compare equal interrupt.\n
*
* \return None.
*
**/
void ECAPIntStatusClear(unsigned int baseAdd, unsigned int flag)
{
HWREGH(baseAdd + ECAP_ECCLR) = HWREGH(baseAdd + ECAP_ECCLR) & flag;
}
/**
* \brief This function enables the generation of interrupts if any of
* event interrupt are enable and corresponding event interrupt
* flag is set.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \return None.
*
**/
void ECAPGlobalIntEnable(unsigned int baseAdd)
{
HWREGH(baseAdd + ECAP_ECCLR) |= ECAP_ECCLR_INT;
}
/**
* \brief This function configures ECAP to Continuous mode.
*
* \param baseAdd It is the Memory address of the ECAP instance used.
*
* \return None.\n
*
* This API is valid only if ECAP is configured to Capture Mode.It has
* no significance when ECAP is configured in APWM mode.
**/
void ECAPContinousModeConfig(unsigned int baseAdd)
{
HWREGH(baseAdd + ECAP_ECCTL2) &= ~ECAP_ECCTL2_CONT_ONESHT;
}
//*****************************************************************************
//
// ADC_setMode
//
//*****************************************************************************
void
ADC_setMode(uint32_t base, ADC_Resolution resolution,
ADC_SignalMode signalMode)
{
uint16_t offsetIndex;
uint16_t offsetTrim;
EALLOW;
switch(base)
{
case ADCA_BASE:
offsetIndex = 0U * 4U;
if(*(uint16_t *)ADC_calADCAINL != 0xFFFFU)
{
// Trim function is programmed into OTP, so call it
(*((void (*)(void))ADC_calADCAINL))();
}
else
{
// Do nothing, no INL trim function populated
}
break;
case ADCB_BASE:
offsetIndex = 1U * 4U;
if(*(uint16_t *)ADC_calADCBINL != 0xFFFFU)
{
// Trim function is programmed into OTP, so call it
(*((void (*)(void))ADC_calADCBINL))();
}
else
{
// Do nothing, no INL trim function populated
}
break;
case ADCC_BASE:
offsetIndex = 2U * 4U;
if(*(uint16_t *)ADC_calADCCINL != 0xFFFFU)
{
// Trim function is programmed into OTP, so call it
(*((void (*)(void))ADC_calADCCINL))();
}
else
{
// Do nothing, no INL trim function populated
}
break;
case ADCD_BASE:
offsetIndex = 3U * 4U;
if(*(uint16_t *)ADC_calADCDINL != 0xFFFFU)
{
// Trim function is programmed into OTP, so call it
(*((void (*)(void))ADC_calADCDINL))();
}
else
{
// Do nothing, no INL trim function populated
}
break;
}
// offset trim function is programmed into OTP, so call it
if(*(uint16_t *)ADC_getOffsetTrim != 0xFFFFU)
{
// Calculate the index into OTP table of offset trims and call
// function to return the correct offset trim
offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) +
(2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U));
offsetTrim =
(*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex);
}
else
{
// Offset trim function is not populated, so set offset trim to 0
offsetTrim = 0U;
}
// Apply the resolution and signalMode to the specified ADC.
HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) &
~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE))|
((uint16_t)resolution | (uint16_t)signalMode);
// Also apply the offset trim and, if needed, linearity trim correction.
HWREGH(base + ADC_O_OFFTRIM) = offsetTrim;
if (resolution == ADC_RESOLUTION_12BIT)
{
// 12-bit linearity trim workaround
HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U;
}
EDIS;
}
/**
* \brief This function disables the specified interrups
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param flag It is the value which specifies the interrupts to
* be disabled.\n
*
* flag can take following macros.
*
* ECAP_CEVT1_INT - Enable Capture Event 1 interrupt.\n
* ECAP_CEVT2_INT - Enable Capture Event 2 interrupt.\n
* ECAP_CEVT3_INT - Enable Capture Event 3 interrupt.\n
* ECAP_CEVT4_INT - Enable Capture Event 4 interrupt.\n
* ECAP_CNTOVF_INT - Enable Counter Overflow interrupt.\n
* ECAP_PRDEQ_INT - Enable Period equal interrupt.\n
* ECAP_CMPEQ_INT - Enable Compare equal interrupt.\n
*
* \return None.
*
**/
void ECAPIntDisable(unsigned int baseAdd, unsigned int flag)
{
HWREGH(baseAdd + ECAP_ECEINT) |= flag;
}
//*****************************************************************************
//
//! Initializes the touch screen driver.
//!
//! This function initializes the touch screen driver, beginning the process of
//! reading from the touch screen. This driver uses the following hardware
//! resources:
//!
//! - ADC sample sequence 3
//! - Timer 1 subtimer A
//!
//! \return None.
//
//*****************************************************************************
void
TouchScreenInit(void)
{
//
// Set the initial state of the touch screen driver's state machine.
//
g_ulTSState = TS_STATE_INIT;
//
// Determine which calibration parameter set we will be using.
//
g_plParmSet = g_lTouchParameters[SET_NORMAL];
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
//
// If the SRAM/Flash daughter board is present, select the appropriate
// calibration parameters and reading threshold value.
//
g_plParmSet = g_lTouchParameters[SET_SRAM_FLASH];
g_sTouchMin = 40;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
//
// If the FPGA daughter board is present, select the appropriate
// calibration parameters and reading threshold value.
//
g_plParmSet = g_lTouchParameters[SET_FPGA];
g_sTouchMin = 70;
}
//
// There is no touch screen handler initially.
//
g_pfnTSHandler = 0;
//
// Enable the peripherals used by the touch screen interface.
//
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
ROM_SysCtlPeripheralEnable(TS_P_PERIPH);
ROM_SysCtlPeripheralEnable(TS_N_PERIPH);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
//
// Configure the ADC sample sequence used to read the touch screen reading.
//
ROM_ADCHardwareOversampleConfigure(ADC0_BASE, 4);
ROM_ADCSequenceConfigure(ADC0_BASE, 3, ADC_TRIGGER_TIMER, 0);
ROM_ADCSequenceStepConfigure(ADC0_BASE, 3, 0,
ADC_CTL_CH_YP | ADC_CTL_END | ADC_CTL_IE);
ROM_ADCSequenceEnable(ADC0_BASE, 3);
//
// Enable the ADC sample sequence interrupt.
//
ROM_ADCIntEnable(ADC0_BASE, 3);
ROM_IntEnable(INT_ADC0SS3);
//
// Configure the GPIOs used to drive the touch screen layers.
//
ROM_GPIOPinTypeGPIOOutput(TS_P_BASE, TS_XP_PIN | TS_YP_PIN);
//
// If no daughter board or one which does not rewire the touchscreen
// interface is installed, set up GPIOs to drive the XN and YN signals.
//
if((g_eDaughterType != DAUGHTER_SRAM_FLASH) &&
(g_eDaughterType != DAUGHTER_FPGA))
{
ROM_GPIOPinTypeGPIOOutput(TS_N_BASE, TS_XN_PIN | TS_YN_PIN);
}
ROM_GPIOPinWrite(TS_P_BASE, TS_XP_PIN | TS_YP_PIN, 0x00);
if(g_eDaughterType == DAUGHTER_SRAM_FLASH)
{
HWREGB(LCD_CONTROL_CLR_REG) = LCD_CONTROL_XN | LCD_CONTROL_YN;
}
else if(g_eDaughterType == DAUGHTER_FPGA)
{
HWREGH(LCD_FPGA_CONTROL_CLR_REG) = LCD_CONTROL_XN | LCD_CONTROL_YN;
}
else
{
ROM_GPIOPinWrite(TS_N_BASE, TS_XN_PIN | TS_YN_PIN, 0x00);
}
//
// See if the ADC trigger timer has been configured, and configure it only
// if it has not been configured yet.
//
if((HWREG(TIMER1_BASE + TIMER_O_CTL) & TIMER_CTL_TAEN) == 0)
{
//
// Configure the timer to trigger the sampling of the touch screen
// every millisecond.
//
ROM_TimerConfigure(TIMER1_BASE, (TIMER_CFG_SPLIT_PAIR |
TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC));
ROM_TimerLoadSet(TIMER1_BASE, TIMER_A,
(ROM_SysCtlClockGet() / 1000) - 1);
ROM_TimerControlTrigger(TIMER1_BASE, TIMER_A, true);
//
// Enable the timer. At this point, the touch screen state machine
// will sample and run once per millisecond.
//
ROM_TimerEnable(TIMER1_BASE, TIMER_A);
}
}
/**
* \brief This function returns the status specified interrups
*
* \param baseAdd It is the Memory address of the ECAP instance used.
* \param flag It is the value which specifies the status of interrupts
* to be returned.\n
*
* flag can take following macros.
*
* ECAP_CEVT1_INT - Status of Capture Event 1 interrupt.\n
* ECAP_CEVT2_INT - Status of Capture Event 2 interrupt.\n
* ECAP_CEVT3_INT - Status of Capture Event 3 interrupt.\n
* ECAP_CEVT4_INT - Status of Capture Event 4 interrupt.\n
* ECAP_CNTOVF_INT - Status of Counter Overflow interrupt.\n
* ECAP_PRDEQ_INT - Status of Period equal interrupt.\n
* ECAP_CMPEQ_INT - Status of Compare equal interrupt.\n
* ECAP_GLOBAL_INT - Global interrupt status.\n
*
* \returns Status of the specified interrupts.
*
**/
unsigned int ECAPIntStatus(unsigned int baseAdd, unsigned int flag)
{
return (HWREGH(baseAdd + ECAP_ECFLG) & flag);
}
