/*FUNCTION********************************************************************** * * Function Name : GPIO_HAL_SetPinDir * Description : Set individual gpio pin to general input or output. * *END**************************************************************************/ void GPIO_HAL_SetPinDir(uint32_t baseAddr, uint32_t pin, gpio_pin_direction_t direction) { assert(pin < 32); if (direction == kGpioDigitalOutput) { HW_GPIO_PDDR_SET(baseAddr, 1U << pin); } else { HW_GPIO_PDDR_CLR(baseAddr, 1U << pin); } }
/*FUNCTION********************************************************************** * * Function Name : GPIO_HAL_SetPinDir * Description : Set individual gpio pin to general input or output. * *END**************************************************************************/ void GPIO_HAL_SetPinDir(uint32_t baseAddr, uint32_t pin, gpio_pin_direction_t direction) { //assert(pin < 32); Apermingeat: this assert call from Freescale KSDK must be adapted to CIAA assert if (direction == kGpioDigitalOutput) { HW_GPIO_PDDR_SET(baseAddr, 1U << pin); } else { HW_GPIO_PDDR_CLR(baseAddr, 1U << pin); } }
static int32_t bsp_usb_otg_io_init ( int32_t i ) { if (i == 0) { #if (OS_ADAPTER_ACTIVE_OS == OS_ADAPTER_MQX) #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ //HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from IRC 48MHz */ //HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); /* Enable USB-OTG IP clocking */ //HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */ //HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from PLL */ //HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK); SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01)); /* Enable USB-OTG IP clocking */ //HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); #endif #else #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from IRC 48MHz */ HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK); /* Enable USB-OTG IP clocking */ HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */ HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK); /* Configure USB to be clocked from PLL */ HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01)); /* Enable USB-OTG IP clocking */ HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK); #endif /* Weak pull downs */ HW_USB_USBCTRL_WR(0x40); #if KHCICFG_HOST_PORT_NATIVE /* Souce the P5V0_K22_USB. Set PTC9 to high */ BW_PORT_PCRn_MUX(HW_PORTC, 9, 1); /* GPIO mux */ HW_GPIO_PDDR_SET(2, 1<<9); /* Set output */ HW_GPIO_PSOR_SET(2, 1<<9); /* Output high */ #endif #endif } else { return -1; /* unknow controller */ } return 0; }