void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
PW_test00_0_dst_u0_data.write_addr(0);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[0][4] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[1][4] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][0] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][1] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][2] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][3] = ((int32_t)0x0015f6080d6fd5c0LL);
PW_test00_0_dst_u0_data.test00_0_dst_v0_data[2][4] = ((int32_t)0x0015f6080d6fd5c0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_u0_data(PR_memAddr + 0, 0);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_u0_data(PR_memAddr + 0, 0);
P_test00_0_dst_u0_data_RdAddr1 = (ht_uint1)0;
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[0][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[1][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][0] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][1] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][2] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][3] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v0_data[2][4] != ((int32_t)(ht_int32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
if (PR_test00_0_dst_u0_data.test00_0_dst_v1_data != ((uint32_t)(ht_uint32)0x000000000d6fd5c0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
S_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][0] = ((int64_t)0x001f7a58947f5200LL);
S_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][1] = ((int64_t)0x001f7a58947f5200LL);
S_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][2] = ((int64_t)0x001f7a58947f5200LL);
S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][0] = ((uint16_t)0x0019fc3898d606e0LL);
S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][1] = ((uint16_t)0x0019fc3898d606e0LL);
S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][2] = ((uint16_t)0x0019fc3898d606e0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_s0_data(PR_memAddr + 0, 1, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_s0_data(PR_memAddr + 0, 1, 0, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int64_t)SR_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][0] != ((int64_t)0x001f7a58947f5200LL)) {
HtAssert(0, 0);
}
if ((int64_t)SR_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][1] != ((int64_t)0x001f7a58947f5200LL)) {
HtAssert(0, 0);
}
if ((int64_t)SR_test00_0_src_s0_data[1][0].test00_0_src_v0_data[0][2] != ((int64_t)0x001f7a58947f5200LL)) {
HtAssert(0, 0);
}
if ((uint16_t)S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][0] != ((uint16_t)0x0019fc3898d606e0LL)) {
HtAssert(0, 0);
}
if ((uint16_t)S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][1] != ((uint16_t)0x0019fc3898d606e0LL)) {
HtAssert(0, 0);
}
if ((uint16_t)S_test00_0_src_s0_data[1][0].test00_0_src_v1_data[0][2] != ((uint16_t)0x0019fc3898d606e0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersBcm::PersBcm()
{
if (PR1_htValid) {
switch (PR1_htInst) {
// Initial Entry Point from Host Code -> BCM_ENTRY
//
// Read in Task information
// GR_task -> midState[8]/data[3]/initNonce/lastNonce/target[3]
case BCM_ENTRY: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_task(PR1_pBcmTask);
ReadMemPause(BCM_TASK_VALID);
}
break;
// Force initial task to be valid
// Setup initial Nonce
case BCM_TASK_VALID: {
S_bTaskValid = true;
S_nonce = S_task.m_initNonce;
S_hashCount = 0;
HtContinue(BCM_CHK_RTN);
}
break;
// Main hash loop, sit and check the result queue
case BCM_CHK_RTN: {
if (SendReturnBusy_bcm() || SendHostMsgBusy()) {
HtRetry();
break;
}
if (S_hashCount > 1000000) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
if (S_nonceHitQue.empty()) {
// No results waiting
if (S_bTaskValid) {
HtContinue(BCM_CHK_RTN);
} else {
if (S_hashCount > 0) {
SendHostMsg(BCM_HASHES_COMPLETED, (ht_uint56)S_hashCount);
S_hashCount = 0;
}
SendReturn_bcm(P1_pBcmTask);
}
} else {
// Results are waiting to be processed
if (S_bcmRsltQue.empty())
HtContinue(BCM_CHK_RTN);
else
HtContinue(BCM_WR_RSLT1);
}
// Reset index for results to zero (for writing to memory)
S_rsltQwIdx = 0;
}
break;
// BCM_WR_RSLT1->3, steps to write a result to memory
case BCM_WR_RSLT1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (S_rsltQwIdx << 3);
WriteMem(memAddr, S_task.m_qw[S_rsltQwIdx]);
S_rsltQwIdx += 1;
if (S_rsltQwIdx < 5)
HtContinue(BCM_WR_RSLT1);
else
HtContinue(BCM_WR_RSLT2);
}
break;
case BCM_WR_RSLT2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
ht_uint48 memAddr = S_bcmRsltQue.front() | (5 << 3);
ht_uint64 memData;
memData(31, 0) = S_task.m_qw[5] & 0xffffffff;
memData(63, 32) = BcmByteSwap32(S_nonceHitQue.front());
S_nonceHitQue.pop();
WriteMem(memAddr, memData);
WriteMemPause(BCM_WR_RSLT3);
}
break;
case BCM_WR_RSLT3: {
if (SendHostMsgBusy()) {
HtRetry();
break;
}
SendHostMsg(BCM_RSLT_BUF_RDY, (ht_uint56)S_bcmRsltQue.front());
S_bcmRsltQue.pop();
HtContinue(BCM_CHK_RTN);
}
break;
default:
assert(0);
}
}
// temps used within macros
uint32_t temp1, temp2, tmp;
// Input Valid Signal reflects Task Valid Signal
T1_vld = S_bTaskValid;
// *** State Setup ***
// Setup T1_data
T1_data.m_dw[0] = S_task.m_data[0];
T1_data.m_dw[1] = S_task.m_data[1];
T1_data.m_dw[2] = S_task.m_data[2];
T1_data.m_dw[3] = S_nonce;
T1_data.m_dw[4] = 0x80000000;
T1_data.m_dw[5] = 0x00000000;
T1_data.m_dw[6] = 0x00000000;
T1_data.m_dw[7] = 0x00000000;
T1_data.m_dw[8] = 0x00000000;
T1_data.m_dw[9] = 0x00000000;
T1_data.m_dw[10] = 0x00000000;
T1_data.m_dw[11] = 0x00000000;
T1_data.m_dw[12] = 0x00000000;
T1_data.m_dw[13] = 0x00000000;
T1_data.m_dw[14] = 0x00000000;
T1_data.m_dw[15] = 0x00000280;
// Setup T1_state
T1_state.m_state[0] = S_task.m_midState.m_state[0];
T1_state.m_state[1] = S_task.m_midState.m_state[1];
T1_state.m_state[2] = S_task.m_midState.m_state[2];
T1_state.m_state[3] = S_task.m_midState.m_state[3];
T1_state.m_state[4] = S_task.m_midState.m_state[4];
T1_state.m_state[5] = S_task.m_midState.m_state[5];
T1_state.m_state[6] = S_task.m_midState.m_state[6];
T1_state.m_state[7] = S_task.m_midState.m_state[7];
// Nonce
T1_nonce = S_nonce;
// *** Do Work ***
// 64-deep Hash Cycle 1
Q(T2_state, 0, T2_data, 0x428A2F98);
Q(T3_state, 7, T3_data, 0x71374491);
Q(T4_state, 6, T4_data, 0xB5C0FBCF);
Q(T5_state, 5, T5_data, 0xE9B5DBA5);
Q(T6_state, 4, T6_data, 0x3956C25B);
Q(T7_state, 3, T7_data, 0x59F111F1);
Q(T8_state, 2, T8_data, 0x923F82A4);
Q(T9_state, 1, T9_data, 0xAB1C5ED5);
Q(T10_state, 0, T10_data, 0xD807AA98);
Q(T11_state, 7, T11_data, 0x12835B01);
Q(T12_state, 6, T12_data, 0x243185BE);
Q(T13_state, 5, T13_data, 0x550C7DC3);
Q(T14_state, 4, T14_data, 0x72BE5D74);
Q(T15_state, 3, T15_data, 0x80DEB1FE);
Q(T16_state, 2, T16_data, 0x9BDC06A7);
Q(T17_state, 1, T17_data, 0xC19BF174);
R(T18_state, 0, T18_data, 0xE49B69C1);
R(T19_state, 7, T19_data, 0xEFBE4786);
R(T20_state, 6, T20_data, 0x0FC19DC6);
R(T21_state, 5, T21_data, 0x240CA1CC);
R(T22_state, 4, T22_data, 0x2DE92C6F);
R(T23_state, 3, T23_data, 0x4A7484AA);
R(T24_state, 2, T24_data, 0x5CB0A9DC);
R(T25_state, 1, T25_data, 0x76F988DA);
R(T26_state, 0, T26_data, 0x983E5152);
R(T27_state, 7, T27_data, 0xA831C66D);
R(T28_state, 6, T28_data, 0xB00327C8);
R(T29_state, 5, T29_data, 0xBF597FC7);
R(T30_state, 4, T30_data, 0xC6E00BF3);
R(T31_state, 3, T31_data, 0xD5A79147);
R(T32_state, 2, T32_data, 0x06CA6351);
R(T33_state, 1, T33_data, 0x14292967);
R(T34_state, 0, T34_data, 0x27B70A85);
R(T35_state, 7, T35_data, 0x2E1B2138);
R(T36_state, 6, T36_data, 0x4D2C6DFC);
R(T37_state, 5, T37_data, 0x53380D13);
R(T38_state, 4, T38_data, 0x650A7354);
R(T39_state, 3, T39_data, 0x766A0ABB);
R(T40_state, 2, T40_data, 0x81C2C92E);
R(T41_state, 1, T41_data, 0x92722C85);
R(T42_state, 0, T42_data, 0xA2BFE8A1);
R(T43_state, 7, T43_data, 0xA81A664B);
R(T44_state, 6, T44_data, 0xC24B8B70);
R(T45_state, 5, T45_data, 0xC76C51A3);
R(T46_state, 4, T46_data, 0xD192E819);
R(T47_state, 3, T47_data, 0xD6990624);
R(T48_state, 2, T48_data, 0xF40E3585);
R(T49_state, 1, T49_data, 0x106AA070);
R(T50_state, 0, T50_data, 0x19A4C116);
R(T51_state, 7, T51_data, 0x1E376C08);
R(T52_state, 6, T52_data, 0x2748774C);
R(T53_state, 5, T53_data, 0x34B0BCB5);
R(T54_state, 4, T54_data, 0x391C0CB3);
R(T55_state, 3, T55_data, 0x4ED8AA4A);
R(T56_state, 2, T56_data, 0x5B9CCA4F);
R(T57_state, 1, T57_data, 0x682E6FF3);
R(T58_state, 0, T58_data, 0x748F82EE);
R(T59_state, 7, T59_data, 0x78A5636F);
R(T60_state, 6, T60_data, 0x84C87814);
R(T61_state, 5, T61_data, 0x8CC70208);
R(T62_state, 4, T62_data, 0x90BEFFFA);
R(T63_state, 3, T63_data, 0xA4506CEB);
R(T64_state, 2, T64_data, 0xBEF9A3F7);
R(T65_state, 1, T65_data, 0xC67178F2);
// Add following hash cycle 1
T66_state.m_state[0] = T66_state.m_state[0] + S_task.m_midState.m_state[0];
T66_state.m_state[1] = T66_state.m_state[1] + S_task.m_midState.m_state[1];
T66_state.m_state[2] = T66_state.m_state[2] + S_task.m_midState.m_state[2];
T66_state.m_state[3] = T66_state.m_state[3] + S_task.m_midState.m_state[3];
T66_state.m_state[4] = T66_state.m_state[4] + S_task.m_midState.m_state[4];
T66_state.m_state[5] = T66_state.m_state[5] + S_task.m_midState.m_state[5];
T66_state.m_state[6] = T66_state.m_state[6] + S_task.m_midState.m_state[6];
T66_state.m_state[7] = T66_state.m_state[7] + S_task.m_midState.m_state[7];
// State Setup
// Setup T67_data
T67_data.m_dw[0] = T67_state.m_state[0];
T67_data.m_dw[1] = T67_state.m_state[1];
T67_data.m_dw[2] = T67_state.m_state[2];
T67_data.m_dw[3] = T67_state.m_state[3];
T67_data.m_dw[4] = T67_state.m_state[4];
T67_data.m_dw[5] = T67_state.m_state[5];
T67_data.m_dw[6] = T67_state.m_state[6];
T67_data.m_dw[7] = T67_state.m_state[7];
T67_data.m_dw[8] = 0x00000000;
T67_data.m_dw[9] = 0x00000000;
T67_data.m_dw[10] = 0x00000000;
T67_data.m_dw[11] = 0x00000000;
T67_data.m_dw[12] = 0x00000000;
T67_data.m_dw[13] = 0x00000000;
T67_data.m_dw[14] = 0x00000000;
T67_data.m_dw[15] = 0x00000000;
T67_data.m_uc[35] = 0x80;
T67_data.m_uc[61] = 0x01;
// Setup T67_state
T67_state.m_state[0] = 0x6A09E667;
T67_state.m_state[1] = 0xBB67AE85;
T67_state.m_state[2] = 0x3C6EF372;
T67_state.m_state[3] = 0xA54FF53A;
T67_state.m_state[4] = 0x510E527F;
T67_state.m_state[5] = 0x9B05688C;
T67_state.m_state[6] = 0x1F83D9AB;
T67_state.m_state[7] = 0x5BE0CD19;
// 64-deep Hash Cycle 2
Q(T68_state, 0, T68_data, 0x428A2F98);
Q(T69_state, 7, T69_data, 0x71374491);
Q(T70_state, 6, T70_data, 0xB5C0FBCF);
Q(T71_state, 5, T71_data, 0xE9B5DBA5);
Q(T72_state, 4, T72_data, 0x3956C25B);
Q(T73_state, 3, T73_data, 0x59F111F1);
Q(T74_state, 2, T74_data, 0x923F82A4);
Q(T75_state, 1, T75_data, 0xAB1C5ED5);
Q(T76_state, 0, T76_data, 0xD807AA98);
Q(T77_state, 7, T77_data, 0x12835B01);
Q(T78_state, 6, T78_data, 0x243185BE);
Q(T79_state, 5, T79_data, 0x550C7DC3);
Q(T80_state, 4, T80_data, 0x72BE5D74);
Q(T81_state, 3, T81_data, 0x80DEB1FE);
Q(T82_state, 2, T82_data, 0x9BDC06A7);
Q(T83_state, 1, T83_data, 0xC19BF174);
R(T84_state, 0, T84_data, 0xE49B69C1);
R(T85_state, 7, T85_data, 0xEFBE4786);
R(T86_state, 6, T86_data, 0x0FC19DC6);
R(T87_state, 5, T87_data, 0x240CA1CC);
R(T88_state, 4, T88_data, 0x2DE92C6F);
R(T89_state, 3, T89_data, 0x4A7484AA);
R(T90_state, 2, T90_data, 0x5CB0A9DC);
R(T91_state, 1, T91_data, 0x76F988DA);
R(T92_state, 0, T92_data, 0x983E5152);
R(T93_state, 7, T93_data, 0xA831C66D);
R(T94_state, 6, T94_data, 0xB00327C8);
R(T95_state, 5, T95_data, 0xBF597FC7);
R(T96_state, 4, T96_data, 0xC6E00BF3);
R(T97_state, 3, T97_data, 0xD5A79147);
R(T98_state, 2, T98_data, 0x06CA6351);
R(T99_state, 1, T99_data, 0x14292967);
R(T100_state, 0, T100_data, 0x27B70A85);
R(T101_state, 7, T101_data, 0x2E1B2138);
R(T102_state, 6, T102_data, 0x4D2C6DFC);
R(T103_state, 5, T103_data, 0x53380D13);
R(T104_state, 4, T104_data, 0x650A7354);
R(T105_state, 3, T105_data, 0x766A0ABB);
R(T106_state, 2, T106_data, 0x81C2C92E);
R(T107_state, 1, T107_data, 0x92722C85);
R(T108_state, 0, T108_data, 0xA2BFE8A1);
R(T109_state, 7, T109_data, 0xA81A664B);
R(T110_state, 6, T110_data, 0xC24B8B70);
R(T111_state, 5, T111_data, 0xC76C51A3);
R(T112_state, 4, T112_data, 0xD192E819);
R(T113_state, 3, T113_data, 0xD6990624);
R(T114_state, 2, T114_data, 0xF40E3585);
R(T115_state, 1, T115_data, 0x106AA070);
R(T116_state, 0, T116_data, 0x19A4C116);
R(T117_state, 7, T117_data, 0x1E376C08);
R(T118_state, 6, T118_data, 0x2748774C);
R(T119_state, 5, T119_data, 0x34B0BCB5);
R(T120_state, 4, T120_data, 0x391C0CB3);
R(T121_state, 3, T121_data, 0x4ED8AA4A);
R(T122_state, 2, T122_data, 0x5B9CCA4F);
R(T123_state, 1, T123_data, 0x682E6FF3);
R(T124_state, 0, T124_data, 0x748F82EE);
R(T125_state, 7, T125_data, 0x78A5636F);
R(T126_state, 6, T126_data, 0x84C87814);
R(T127_state, 5, T127_data, 0x8CC70208);
R(T128_state, 4, T128_data, 0x90BEFFFA);
R(T129_state, 3, T129_data, 0xA4506CEB);
R(T130_state, 2, T130_data, 0xBEF9A3F7);
R(T131_state, 1, T131_data, 0xC67178F2);
// Add following hash cycle 2
T132_state.m_state[0] = BcmByteSwap32(T132_state.m_state[0] + 0x6A09E667);
T132_state.m_state[1] = BcmByteSwap32(T132_state.m_state[1] + 0xBB67AE85);
T132_state.m_state[2] = BcmByteSwap32(T132_state.m_state[2] + 0x3C6EF372);
T132_state.m_state[3] = BcmByteSwap32(T132_state.m_state[3] + 0xA54FF53A);
T132_state.m_state[4] = BcmByteSwap32(T132_state.m_state[4] + 0x510E527F);
T132_state.m_state[5] = BcmByteSwap32(T132_state.m_state[5] + 0x9B05688C);
T132_state.m_state[6] = BcmByteSwap32(T132_state.m_state[6] + 0x1F83D9AB);
T132_state.m_state[7] = BcmByteSwap32(T132_state.m_state[7] + 0x5BE0CD19);
// *** End Checks ***
// Increment Nonce
if (T1_vld)
S_nonce++;
// Send MSG back if we need to!
// Check for Result Found
if (T133_vld && !S_nonceHitQue.full()) {
bool bW7Eq = T133_state.m_state[7] == S_task.m_target[2];
bool bW7Lt = T133_state.m_state[7] < S_task.m_target[2];
bool bW6Eq = T133_state.m_state[6] == S_task.m_target[1];
bool bW6Lt = T133_state.m_state[6] < S_task.m_target[1];
bool bW5Eq = T133_state.m_state[5] == S_task.m_target[0];
bool bW5Lt = T133_state.m_state[5] < S_task.m_target[0];
bool bMatch = bW7Lt || bW7Eq && (bW6Lt || bW6Eq && (bW5Lt || bW5Eq));
if (bMatch)
S_nonceHitQue.push(BcmByteSwap32(T133_nonce));
// Check for Last Nonce / Increment count
if (S_task.m_lastNonce == T133_nonce)
S_bTaskValid = false;
else
S_hashCount++;
}
// Check force return / reset
if (S_forceReturn) {
S_bTaskValid = false;
S_forceReturn = false;
}
if (GR_htReset) {
S_zeroInput = true;
S_bTaskValid = false;
S_forceReturn = false;
}
}
void
CPersVadd::PersVadd()
{
if (PR_htValid) {
switch (PR_htInst) {
case VADD_RESET:
if (SR_msgDelay < 500 || SendHostMsgBusy()) {
S_msgDelay += 1;
HtRetry();
break;
}
SendHostMsg(VADD_TYPE_SIZE, (XDIM_LEN << 8) | TYPE_SIZE);
HtTerminate();
break;
case VADD_ENTER:
S_yIdx[PR_htId] = 0;
S_yDimLen[PR_htId] = PR_yDimLen;
S_xIdx[PR_htId] = 0;
S_xDimLen[PR_htId] = PR_xDimLen;
S_sum[PR_htId] = 0;
P_addrA = SR_addrA + PR_yAddrOff;
P_addrB = SR_addrB + PR_yAddrOff;
P_addrC = SR_addrC + PR_yAddrOff;
HtContinue(VADD_OPEN);
break;
case VADD_OPEN:
// Open read stream A, once for each xDim to be processed
if (PR_yOpenAIdx < PR_yDimLen && !ReadStreamBusy_A(PR_htId)) {
ht_uint32 remLen = (ht_uint32)((PR_yDimLen - PR_yOpenAIdx) * PR_xDimLen);
ReadStreamOpen_A(PR_htId, PR_addrA, remLen > 0x3f ? (ht_uint6)0x3f : (ht_uint6)remLen, P_yOpenAIdx);
P_addrA+= PR_xDimLen * TYPE_SIZE;
P_yOpenAIdx += 1;
}
// Open read stream B, once for each xDim to be processed
if (PR_yOpenBIdx < PR_yDimLen && !ReadStreamBusy_B(PR_htId)) {
ReadStreamOpen_B(PR_htId, PR_addrB, PR_xDimLen);
P_addrB += PR_xDimLen * TYPE_SIZE;
P_yOpenBIdx += 1;
}
// Open write stream, once for each xDim to be processed
if (PR_yOpenCIdx < SR_yDimLen[PR_htId] && !WriteStreamBusy_C(PR_htId)) {
#if VADD_STRM_RSP_GRP_HTID == 0 && VADD_HTID_W == 0 && VADD_RSP_GRP_W > 0
WriteStreamOpen_C(PR_htId, 1u, PR_addrC);
#elif VADD_STRM_RSP_GRP_HTID || VADD_HTID_W == 0
WriteStreamOpen_C(PR_htId, PR_addrC);
#else
WriteStreamOpen_C(PR_htId, PR_htId ^ 1, PR_addrC);
#endif
P_addrC += PR_xDimLen * TYPE_SIZE;
P_yOpenCIdx += 1;
}
if (PR_yOpenAIdx == PR_yDimLen && PR_yOpenBIdx == PR_yDimLen && PR_yOpenCIdx == PR_yDimLen)
#if VADD_STRM_RSP_GRP_HTID == 0 && VADD_HTID_W == 0 && VADD_RSP_GRP_W > 0
WriteStreamPause_C(1, VADD_RETURN);
#elif VADD_STRM_RSP_GRP_HTID || VADD_HTID_W == 0
WriteStreamPause_C(VADD_RETURN);
#else
WriteStreamPause_C(PR_htId ^ 1, VADD_RETURN);
#endif
else
HtContinue(VADD_OPEN);
break;
case VADD_RETURN: {
BUSY_RETRY(SendReturnBusy_htmain());
SendReturn_htmain(S_sum[PR_htId]);
}
break;
default:
assert(0);
}
}
void
CPersStream::PersStream()
{
if (PR_htValid) {
switch (PR_htInst) {
// Main entry point from Main.cpp
// P_rcvAu, P_rcvCnt are populated through call.
case STRM_IDLE:
{
if (SendReturnBusy_htmain()) {
HtRetry();
break;
}
#ifndef _HTV
printf("SysC: AU %2d - Processing\n", P_rcvAu);
#endif
if (P_rcvCnt) {
HtContinue(STRM_RECV);
} else {
// There are no calls to receive...simply return
SendReturn_htmain(0);
}
}
break;
case STRM_RECV:
{
if (RecvHostDataBusy()) {
HtRetry();
break;
}
// Store received data into pricate variable recvData
P_recvData = RecvHostData();
HtContinue(STRM_SEND);
}
break;
case STRM_SEND:
{
if (SendHostDataBusy() || SendReturnBusy_htmain()) {
HtRetry();
break;
}
// Generate an expected value to compare against received data
uint64_t expectedData = 0LL;
expectedData |= (uint64_t)((uint64_t)P_rcvAu << 48);
expectedData |= (uint64_t)(P_wordCnt + 1);
if (expectedData != P_recvData) {
#ifndef _HTV
printf("SysC: WARNING - Expected Data did not match Received data!\n");
printf(" 0x%016llx != 0x%016llx\n",
(unsigned long long)expectedData, (unsigned long long)P_recvData);
#endif
P_errs += 1;
}
HtAssert(!P_errs, 0);
// Send generated data back to the host
// More error checking will be done there
SendHostData(expectedData);
P_wordCnt += 1;
// Check count so far..
// Either return to Main.cpp or continue reading in values
if (P_wordCnt == P_rcvCnt) {
SendReturn_htmain(P_errs);
} else {
HtContinue(STRM_RECV);
}
}
break;
default:
assert(0);
}
}
}
void CPersCtl::PersCtl()
{
if (PR_htValid) {
switch (PR_htInst) {
case CTL_INIT:
{
HtContinue(CTL_A);
}
break;
case CTL_A:
{
if (SendCallBusy_modA()) {
HtRetry();
break;
}
SendCall_modA(CTL_B);
}
break;
case CTL_B:
{
if (SendCallBusy_modB()) {
HtRetry();
break;
}
SendCall_modB(CTL_C);
}
break;
case CTL_C:
{
if (SendCallBusy_modC()) {
HtRetry();
break;
}
SendCall_modC(CTL_D);
}
break;
case CTL_D:
{
if (SendCallBusy_modD()) {
HtRetry();
break;
}
SendCall_modD(CTL_E);
}
break;
case CTL_E:
{
if (SendCallBusy_modE()) {
HtRetry();
break;
}
SendCall_modE(CTL_SEND_MSG);
}
break;
case CTL_SEND_MSG:
{
if (SendMsgBusy_CtlToA(2)) {
HtRetry();
break;
}
S_msgRcvd = false;
// Send messages to modA
SendMsg_CtlToA(2, 0);
HtContinue(CTL_RTN);
}
break;
case CTL_RTN:
{
if (SendReturnBusy_htmain()) {
HtRetry();
break;
}
if (!S_msgRcvd) {
HtRetry();
break;
}
// Return to host interface
SendReturn_htmain(P_elemCnt);
}
break;
default:
assert(0);
}
}
if (!GR_htReset && !RecvMsgBusy_EtoCtl()) {
ht_uint4 msg = RecvMsg_EtoCtl();
HtAssert(msg == 0, msg);
S_msgRcvd = msg == 0;
}
}
void CPersTest00::PersTest00() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_u0_data(PR1_memAddr + 0, 6, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_u0_data(PR1_memAddr + 0, 0, 0, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((ht_uint8)PR1_test00_0_src_u0_data[0].test00_0_src_v0_data[0] != ((ht_uint8)0x0000000000000060LL)) {
HtAssert(0, 0);
}
if ((ht_int64)PR1_test00_0_src_u0_data[0].test00_0_src_v1_data != ((ht_int64)0x0015d74eb55d5960LL)) {
printf("EXP - v1 = 0x%016lx\n", (int64_t)0x0015d74eb55d5960LL);
printf("ACT - v1 = 0x%016lx\n", (int64_t)PR1_test00_0_src_u0_data[0].test00_0_src_v1_data);
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
if (PR5_htValid) {
switch (PR5_htInst) {
case TEST00_ENTRY: {
break;
}
case TEST00_WR: {
PW5_test00_0_src_u0_data[0].write_addr(6);
PW5_test00_0_src_u0_data[0].test00_0_src_v1_data = ((int64_t)0x0015d74eb55d5960LL);
break;
}
case TEST00_ST0: {
break;
}
case TEST00_LD0: {
P5_test00_0_src_u0_data_RdAddr1 = (ht_uint3)0;
break;
}
case TEST00_CHK: {
break;
}
case TEST00_RTN: {
break;
}
default:
assert(0);
}
}
}
void CPersProcess::PersProcess() {
if (PR_htValid) {
switch (PR_htInst) {
// Main Entry Point from PersCtl_src.cpp -> PROCESS_ENTRY
// Calculate the number of multiplies we need to do and store in P_calcLen
// Dispatch threads to do a muliply operation for that index
// Continue spawning multiply threads until P_calcIdx == P_calcLen, at which point
// wait for all threads to return before continuing to PROCESS_STORE
case PROCESS_ENTRY: {
if (SendCallBusy_mult()) {
HtRetry();
break;
}
P_calcLen = ((P_rcvIdx+1) < SR_numTaps) ? (P_rcvIdx+1) : SR_numTaps;
if (P_calcIdx < P_calcLen) {
SendCallFork_mult(PROCESS_JOIN, P_rcvIdx, P_calcIdx);
HtContinue(PROCESS_ENTRY);
P_calcIdx += 1;
} else {
RecvReturnPause_mult(PROCESS_STORE);
}
}
break;
// Join spawned Mult threads
// Sum Returned data from P_result into P_sum to later be stored to memory
// Accumulate errors from the returning thread
case PROCESS_JOIN: {
P_sum += P_result;
P_errs += P_errRcv;
RecvReturnJoin_mult();
}
break;
// Store P_sum into memory as an output of the FIR Filter
// This is one element (index) in the entire output
// Issue Write Request and wait until complete, then continue to PROCESS_RTN
case PROCESS_STORE: {
if (WriteMemBusy()) {
HtRetry();
break;
}
MemAddr_t memWrAddr = (ht_uint48)(SR_outAddrBase + (P_rcvIdx << 3));
WriteMem(memWrAddr, P_sum);
WriteMemPause(PROCESS_RTN);
}
break;
// Done with work for this Index
// Return to CTL to echo the Index to the Host and accumulate errors
case PROCESS_RTN: {
if (SendReturnBusy_process()) {
HtRetry();
break;
}
SendReturn_process(P_rcvIdx, P_errs);
}
break;
default:
assert(0);
}
}
}
void CPersGv1::PersGv1()
{
if (PR_htValid) {
switch (PR_htInst) {
case GV1_ENTRY:
{
P_x = PR_htId;
P_gvAddr = PR_htId;
P_gvAddr2 = 0u;
P_gvAddr3 = 0u;
// D_1x
GW_gv_D_1x_1F_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_m0.m_x = P_x;
GW_gv_D_1x_1F_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_m1.m_x = P_x;
GW_gv_D_1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x_1F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_AI_m0.m_x = P_x;
GW_gv_D_1x_1F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_AI_m1.m_x = P_x;
GW_gv_D_1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x_2F_AI_m0.m_x[0] = P_x;
GW_gv_D_1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x_2F_AI_m1.m_x[0] = P_x;
GW_gv_D_1x_1F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_AA_m0.m_x = P_x;
GW_gv_D_1x_1F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x_4F_AA_m0.m_x[0] = P_x;
GW_gv_D_1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x
GW_gv_D_1x1x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_m0.m_x = P_x;
GW_gv_D_1x1x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_m1.m_x = P_x;
GW_gv_D_1x1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AI_m0.m_x = P_x;
GW_gv_D_1x1x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AI_m1.m_x = P_x;
GW_gv_D_1x1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x_2F_AI_m0.m_x[0] = P_x;
GW_gv_D_1x1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x_2F_AI_m1.m_x[0] = P_x;
GW_gv_D_1x1x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AA_m0.m_x = P_x;
GW_gv_D_1x1x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x_4F_AA_m0.m_x[0] = P_x;
GW_gv_D_1x1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x1x
GW_gv_D_1x1x1x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_m0.m_x = P_x;
GW_gv_D_1x1x1x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_m1.m_x = P_x;
GW_gv_D_1x1x1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x1x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AI_m0.m_x = P_x;
GW_gv_D_1x1x1x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AI_m1.m_x = P_x;
GW_gv_D_1x1x1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_AI_m0.m_x[0] = P_x;
GW_gv_D_1x1x1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_AI_m1.m_x[0] = P_x;
GW_gv_D_1x1x1x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AA_m0.m_x = P_x;
GW_gv_D_1x1x1x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_4F_AA_m0.m_x[0] = P_x;
GW_gv_D_1x1x1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x2x2x
GW_gv_D_1x1x2x2x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_m0.m_x = P_x;
GW_gv_D_1x1x2x2x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_m1.m_x = P_x;
GW_gv_D_1x1x2x2x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AI_m0.m_x = P_x;
GW_gv_D_1x1x2x2x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AI_m1.m_x = P_x;
GW_gv_D_1x1x2x2x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_AI_m0.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_AI_m1.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AA_m0.m_x = P_x;
GW_gv_D_1x1x2x2x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x2x2x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_4F_AA_m0.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_4F_AA_m1.m_x[0] = P_x;
P_loopCnt = 0;
HtContinue(GV1_LOOP);
}
break;
case GV1_LOOP:
{
// D_1x
if (GR_gv_D_1x_1F_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_1F_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_2F_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_2F_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_1F_AI_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_1F_AI_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_2F_AI_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_2F_AI_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_1F_AA_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_1F_AA_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_4F_AA_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x_4F_AA_m1.m_x[0] != PR_x) HtAssert(0, 0);
// D_1x1x
if (GR_gv_D_1x1x_1F_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_1F_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_2F_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_2F_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_1F_AI_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_1F_AI_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_2F_AI_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_2F_AI_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_1F_AA_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_1F_AA_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_4F_AA_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x_4F_AA_m1.m_x[0] != PR_x) HtAssert(0, 0);
// D_1x1x1x
if (GR_gv_D_1x1x1x_1F_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_1F_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_2F_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_2F_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_1F_AI_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_1F_AI_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_2F_AI_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_2F_AI_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_1F_AA_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_1F_AA_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_4F_AA_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x1x_4F_AA_m1.m_x[0] != PR_x) HtAssert(0, 0);
// D_1x1x2x2x
if (GR_gv_D_1x1x2x2x_1F_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_1F_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_2F_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_2F_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_1F_AI_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_1F_AI_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_2F_AI_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_2F_AI_m1.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_1F_AA_m0.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_1F_AA_m1.m_x != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_4F_AA_m0.m_x[0] != PR_x) HtAssert(0, 0);
if (GR_gv_D_1x1x2x2x_4F_AA_m1.m_x[0] != PR_x) HtAssert(0, 0);
P_x += 1;
// D_1x
GW_gv_D_1x_1F_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_m0.m_x = P_x;
GW_gv_D_1x_1F_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_m1.m_x = P_x;
GW_gv_D_1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x_1F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_AI_m0.m_x.AtomicInc();
GW_gv_D_1x_1F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_AI_m1.m_x.AtomicInc();
GW_gv_D_1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x_2F_AI_m0.m_x[0].AtomicInc();
GW_gv_D_1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x_2F_AI_m1.m_x[0].AtomicInc();
GW_gv_D_1x_1F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x_1F_AA_m0.m_x.AtomicAdd(1u);
GW_gv_D_1x_1F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x_4F_AA_m0.m_x[0].AtomicAdd(1u);
GW_gv_D_1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x
GW_gv_D_1x1x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_m0.m_x = P_x;
GW_gv_D_1x1x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_m1.m_x = P_x;
GW_gv_D_1x1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AI_m0.m_x.AtomicInc();
GW_gv_D_1x1x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AI_m1.m_x.AtomicInc();
GW_gv_D_1x1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x_2F_AI_m0.m_x[0].AtomicInc();
GW_gv_D_1x1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x_2F_AI_m1.m_x[0].AtomicInc();
GW_gv_D_1x1x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AA_m0.m_x.AtomicAdd(1u);
GW_gv_D_1x1x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x_4F_AA_m0.m_x[0].AtomicAdd(1u);
GW_gv_D_1x1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x1x
GW_gv_D_1x1x1x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_m0.m_x = P_x;
GW_gv_D_1x1x1x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_m1.m_x = P_x;
GW_gv_D_1x1x1x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x1x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x1x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AI_m0.m_x.AtomicInc();
GW_gv_D_1x1x1x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AI_m1.m_x.AtomicInc();
GW_gv_D_1x1x1x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_AI_m0.m_x[0].AtomicInc();
GW_gv_D_1x1x1x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_2F_AI_m1.m_x[0].AtomicInc();
GW_gv_D_1x1x1x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AA_m0.m_x.AtomicAdd(1u);
GW_gv_D_1x1x1x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x1x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x1x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x1x_4F_AA_m0.m_x[0].AtomicAdd(1u);
GW_gv_D_1x1x1x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x1x_4F_AA_m1.m_x[0] = P_x;
// D_1x1x2x2x
GW_gv_D_1x1x2x2x_1F_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_m0.m_x = P_x;
GW_gv_D_1x1x2x2x_1F_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_m1.m_x = P_x;
GW_gv_D_1x1x2x2x_2F_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_m0.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_2F_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_m1.m_x[0] = P_x;
GW_gv_D_1x1x2x2x_1F_AI_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AI_m0.m_x.AtomicInc();
GW_gv_D_1x1x2x2x_1F_AI_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AI_m1.m_x.AtomicInc();
GW_gv_D_1x1x2x2x_2F_AI_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_AI_m0.m_x[0].AtomicInc();
GW_gv_D_1x1x2x2x_2F_AI_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_2F_AI_m1.m_x[0].AtomicInc();
GW_gv_D_1x1x2x2x_1F_AA_m0.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AA_m0.m_x.AtomicAdd(1u);
GW_gv_D_1x1x2x2x_1F_AA_m1.write_addr(PR_htId, 0u);
GW_gv_D_1x1x2x2x_1F_AA_m1.m_x = P_x;
GW_gv_D_1x1x2x2x_4F_AA_m0.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_4F_AA_m0.m_x[0].AtomicAdd(1u);
GW_gv_D_1x1x2x2x_4F_AA_m1.write_addr(PR_htId);
GW_gv_D_1x1x2x2x_4F_AA_m1.m_x[0] = P_x;
HtContinue(P_loopCnt++ < 100 ? GV1_LOOP : GV1_RETURN);
}
break;
case GV1_RETURN:
{
if (SendReturnBusy_gv1()) {
HtRetry();
break;
}
SendReturn_gv1();
}
break;
default:
assert(0);
}
}
}
void
CPersInc::PersInc()
{
if (PR_htValid) {
switch (PR_htInst) {
case INC_INIT:
{
P_loopCnt = 0;
P_reqCnt = 0;
// Set address for reading memory response data
P_arrayMemRdPtr = PR_htId;
HtContinue(INC_READ);
}
break;
case INC_READ:
{
if (ReadMemBusy() || SendReturnBusy_htmain()) {
HtRetry();
break;
}
// Check if end of loop
if (P_loopCnt == P_elemCnt) {
// Return to host interface
SendReturn_htmain(P_loopCnt);
} else {
// Calculate memory read address
sc_uint<MEM_ADDR_W> memRdAddr = (sc_uint<MEM_ADDR_W>)(SR_arrayAddr + (((P_loopCnt + P_reqCnt) * 2) << 3));
sc_uint<2> rdDstId = P_reqCnt;
bool bLast = P_reqCnt == 3;
// Issue read request to memory
switch (rdDstId) {
case 0:
ReadMem_arrayMem1Fld1(memRdAddr, PR_htId);
break;
case 1:
ReadMem_arrayMem1Fld2(memRdAddr, PR_htId);
break;
case 2:
ReadMem_arrayMem2Fld1(memRdAddr, PR_htId);
break;
case 3:
ReadMem_arrayMem2Fld2(memRdAddr, PR_htId);
break;
}
if (bLast) {
P_reqCnt = 0;
ReadMemPause(INC_WRITE);
} else {
P_reqCnt += 1;
HtContinue(INC_READ);
}
}
}
break;
case INC_WRITE:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = 0;
sc_uint<2> rdDstId = P_reqCnt;
switch (rdDstId) {
case 0:
memWrData = GR_arrayMem1.fld1 + 1;
break;
case 1:
memWrData = GR_arrayMem1.fld2 + 1;
break;
case 2:
memWrData = GR_arrayMem2.fld1 + 1;
break;
case 3:
memWrData = GR_arrayMem2.fld2 + 1;
break;
}
// Calculate memory write address
sc_uint<MEM_ADDR_W> memWrAddr = (sc_uint<MEM_ADDR_W>)(SR_arrayAddr + (((P_loopCnt + P_reqCnt) * 2 + 1) << 3));
bool bLast = P_reqCnt == 3;
// Issue write memory request
WriteMem(memWrAddr, memWrData);
if (bLast) {
// Increment loop count
P_loopCnt = P_loopCnt + 4;
P_reqCnt = 0;
WriteMemPause(INC_READ);
} else {
P_reqCnt += 1;
HtContinue(INC_WRITE);
}
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
GW1_test00_0_dst_s0_data[0][0].write_addr(14, 13);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[0][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[1][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[2][0] = ((uint8_t)0x001af188b6cf7780LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v1_data = ((uint32_t)0x001de80faced6660LL);
GW1_test00_0_dst_s0_data[0][0].test00_0_dst_v2_data = ((int64_t)0x0002809850655dc0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_s0_data(PR1_memAddr + 0, 0, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_s0_data(PR1_memAddr + 0, 6, 5, 0, 1);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[0][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[1][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v0_data[2][0] != ((uint8_t)0x001af188b6cf7780LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v1_data != ((uint32_t)0x001de80faced6660LL)) {
HtAssert(0, 0);
}
if (GR1_test00_0_dst_s0_data[0][0].test00_0_dst_v2_data != ((int64_t)0x0002809850655dc0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
if (PR2_htValid) {
switch (PR2_htInst) {
case TEST00_ENTRY: {
break;
}
case TEST00_WR0: {
break;
}
case TEST00_ST0: {
break;
}
case TEST00_LD0: {
P2_test00_0_dst_s0_data_RdAddr1 = (ht_uint4)6;
P2_test00_0_dst_s0_data_RdAddr2 = (ht_uint5)5;
break;
}
case TEST00_CHK0: {
break;
}
case TEST00_RTN: {
break;
}
default:
assert(0);
}
}
}
void CPersWr4::PersWr4()
{
if (PR_htValid) {
switch (PR_htInst) {
case WR4_INIT:
{
P_loopCnt = 0;
P_err = 0;
P_pauseLoopCnt = 0;
HtContinue(WR4_WRITE1b);
}
break;
case WR4_WRITE1a:
case WR4_WRITE1b:
{
if (PR_htInst != (PR_pauseDst ? WR4_WRITE1a : WR4_WRITE1b)) {
HtAssert(0, 0);
P_err += 1;
}
P_pauseDst ^= 1;
if (WriteMemBusy() || SendReturnBusy_wr4()) {
HtRetry();
break;
}
// Check if end of loop
if (P_loopCnt == PAUSE_LOOP_CNT || P_err) {
// Return to host interface
SendReturn_wr4(P_err);
} else {
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + ((P_loopCnt & 0xf) << 3);
// Issue read request to memory
WriteMem(memRdAddr, (P_loopCnt & 0xf));
// Set address for reading memory response data
HtContinue(WR4_WRITE2);
}
}
break;
case WR4_WRITE2:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 1) & 0xf) << 3);
// Issue read request to memory
WriteMem(memRdAddr, ((P_loopCnt + 1) & 0xf));
HtContinue(WR4_WRITE3);
}
break;
case WR4_WRITE3:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 2) & 0xf) << 3);
// Issue read request to memory
WriteMem(memRdAddr, ((P_loopCnt + 2) & 0xf));
HtContinue(WR4_WRITE4);
}
break;
case WR4_WRITE4:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 3) & 0xf) << 3);
// Issue read request to memory
WriteMem(memRdAddr, ((P_loopCnt + 3) & 0xf));
HtContinue(WR4_LOOP);
}
break;
case WR4_LOOP:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// wait a few instructions for last response to line up with call to ReadMemPause
if (P_pauseLoopCnt == 0) {
P_pauseLoopCnt = 0;
P_loopCnt += 1;
if (PR_pauseDst)
WriteMemPause(WR4_WRITE1a);
else
WriteMemPause(WR4_WRITE1b);
} else {
P_pauseLoopCnt += 1;
HtContinue(WR4_LOOP);
}
}
break;
default:
assert(0);
}
}
#ifndef _HTV
if (r_m1_wrRspRdy) {
#if (WR4_HTID_W == 0)
if (!r_wrGrpRsmWait)
printf("-");
else if (r_wrGrpRspCnt == 1)
printf("1");
else
printf("+");
#else
#if (WR4_HTID_W < 2)
if (!r_wrGrpRsmWait[INT(r_m1_wrRspTid & ((1 << WR2_WR_GRP_ID_W) - 1))])
printf("-");
else if (r_wrGrpRspCnt[INT(r_m1_wrRspTid & ((1 << WR2_WR_GRP_ID_W) - 1))] == 1)
printf("4");
else
printf("+");
#else
{
m_wrGrpReqState1.read_addr(r_m1_wrGrpId);
m_wrGrpRspState0.read_addr(r_m1_wrGrpId);
CWrGrpRspState c_m1_wrGrpRspState = m_wrGrpRspState0.read_mem();
CWrGrpReqState c_m1_wrGrpReqState = m_wrGrpReqState1.read_mem();
if (c_m1_wrGrpReqState.m_pause != c_m1_wrGrpRspState.m_pause)
printf("-");
else if (c_m1_wrGrpReqState.m_cnt - c_m1_wrGrpRspState.m_cnt == 1)
printf("4");
else
printf("+");
}
#endif
#endif
}
#endif
}
void CPersRd::PersRd() {
if (PR_htValid) {
switch (PR_htInst) {
case RD_ENTRY: {
P_bStandalonePause = false;
P_reqIdx = 0;
P_loopIdx = 0;
P_memOffset = PR_threadId;
HtBarrier(RD_REQ, 8);
break;
}
case RD_REQ: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ht_uint5 elemCnt = ((PR_threadId + PR_reqIdx) & 7) + 1;
if (PR_memOffset + elemCnt + PR_threadId >= 256)
P_memOffset = PR_threadId;
ht_uint8 info = PR_threadId + P_memOffset;
ht_uint48 addr = PR_memAddr + P_memOffset * 8;
ReadMem_rdFunc(addr, info, elemCnt);
P_memOffset += elemCnt;
if (PR_reqIdx == 7) {
if (PR_bStandalonePause) {
HtContinue(RD_PAUSE);
} else {
ReadMemPause(RD_LOOP);
}
P_bStandalonePause ^= 1;
P_reqIdx = 0;
} else {
P_reqIdx += 1;
HtContinue(RD_REQ);
}
break;
}
case RD_PAUSE: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMemPause(RD_LOOP);
break;
}
case RD_LOOP: {
if (PR_loopIdx == 255) {
HtContinue(RD_RTN);
} else {
HtContinue(RD_REQ);
}
P_loopIdx += 1;
break;
}
case RD_RTN: {
if (SendReturnBusy_rdPause()) {
HtRetry();
break;
}
SendReturn_rdPause();
break;
}
default:
assert(0);
}
}
}
void CPersRdSub::PersRdSub()
{
if (PR_htValid) {
switch (PR_htInst) {
case WS_READ:
{
#ifndef _HTV
entryMask |= 1 << PR_htId;
#endif
if (
#ifndef _HTV
entryMask != ((1ull << (1 << WS_HTID_W))-1) ||
#endif
ReadMemBusy()) {
HtRetry();
break;
}
switch (P_rdType) {
case 0:
ReadMem_uint8(P_rdAddr, PR_htId);
break;
case 1:
ReadMem_uint16(P_rdAddr, PR_htId);
break;
case 2:
ReadMem_uint32(P_rdAddr, PR_htId);
break;
case 3:
ReadMem_uint64(P_rdAddr, PR_htId);
break;
case 4:
ReadMem_int8(P_rdAddr, PR_htId);
break;
case 5:
ReadMem_int16(P_rdAddr, PR_htId);
break;
case 6:
ReadMem_int32(P_rdAddr, PR_htId);
break;
case 7:
ReadMem_int64(P_rdAddr, PR_htId);
break;
default:
assert(0);
}
ReadMemPause(WS_RETURN);
}
break;
case WS_RETURN:
{
if (SendReturnBusy_RdSub()) {
HtRetry();
break;
}
SendReturn_RdSub(S_actual[PR_htId], P_expected);
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
PW_test00_0_src_v0_data[0].write_addr(4, 7);
PW_test00_0_src_v0_data[0] = ((int16_t)0x000e9de7ebf4aec0LL);
S_test00_1_dst_s0_data.write_addr(3, 3);
S_test00_1_dst_s0_data.write_mem().test00_1_dst_u0_data.test00_1_dst_u2_data.test00_1_dst_v6_data = ((int16_t)0x000cfb2347be8920LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v0_data(PR_memAddr + 0, 4, 7, 0, 1);
HtContinue(TEST00_ST1);
break;
}
case TEST00_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_1_dst_u2_data(PR_memAddr + 64, 3, 3, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v3_data(PR_memAddr + 0, 0, 1, 1);
HtContinue(TEST00_LD1);
break;
}
case TEST00_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_1_dst_u2_data(PR_memAddr + 64, 3, 3, 1);
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int16_t)PR_test00_0_dst_u0_data[0].test00_0_dst_v3_data[1] != ((int16_t)0x000e9de7ebf4aec0LL)) {
HtAssert(0, 0);
}
SR_test00_1_dst_s0_data.read_addr(3, 3);
printf("EXP: 0x%04x\n", (int16_t)0x000cfb2347be8920LL);
printf("ACT: 0x%04x\n", (int16_t)S_test00_1_dst_s0_data.read_mem().test00_1_dst_u0_data.test00_1_dst_u2_data.test00_1_dst_v6_data);
if ((int16_t)S_test00_1_dst_s0_data.read_mem().test00_1_dst_u0_data.test00_1_dst_u2_data.test00_1_dst_v6_data != ((int16_t)0x000cfb2347be8920LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersInc11::PersInc11()
{
if (PR1_htValid) {
switch (PR1_htInst) {
case INC11_INIT:
{
P1_loopIdx[0][1] = 0;
P1_wrGrpId = PR1_htId ^ 0x5;
// wait until all threads have started
HtContinue(INC11_READ);
}
break;
case INC11_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = SR_arrayAddr + ((P1_loopBase + P1_loopIdx[0][1]) << 3);
Inc11Ptr_t arrayMemWrPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
// Issue read request to memory
ReadMem_arrayMem11(memRdAddr, arrayMemWrPtr);
bool bLast = P1_loopIdx[0][1] == P1_elemCnt - 1;
if (bLast) {
P1_loopIdx[0][1] = 0;
ReadMemPause(INC11_WRITE);
} else {
P1_loopIdx[0][1] += 1;
HtContinue(INC11_READ);
}
// Set address for reading memory response data
P1_arrayMemRdPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
}
break;
case INC11_WRITE:
{
if (WriteMemBusy()) {
//if (WriteMemBusy(wrRspGrpId)) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = GR1_arrayMem11.data + 1;
// Calculate memory write address
MemAddr_t memWrAddr = SR_arrayAddr + ((P1_loopBase + P1_loopIdx[0][1]) << 3);
// Issue write memory request
WriteMem(PR1_wrGrpId, memWrAddr, memWrData);
bool bLast = P1_loopIdx[0][1] == P1_elemCnt - 1;
if (bLast) {
P1_loopIdx[0][1] = 0;
//WriteMemPause(wrRspGrpId, INC11_RTN);
WriteMemPause(PR1_wrGrpId, INC11_RTN);
//HtPause();
} else {
P1_loopIdx[0][1] += 1;
HtContinue(INC11_WRITE);
}
// Set address for reading memory response data
P1_arrayMemRdPtr = (PR1_htId << 7) | P1_loopIdx[0][1];
}
break;
case INC11_RTN:
{
if (SendReturnBusy_inc11()) {
HtRetry();
break;
}
SendReturn_inc11(P1_elemCnt);
break;
}
default:
assert(0);
}
}
}
void
CPersAdd::PersAdd()
{
// Set read address of op1Mem/op2Mem/resMem variables
// These will always be the same in every instruction for each thread
S_op1Mem.read_addr(PR_htId);
S_op2Mem.read_addr(PR_htId);
S_resMem.read_addr(PR_htId);
// Force "Inputs Valid" to default to false unless true in the ADD_PAUSE instruction
P_i_vld = false;
if (PR_htValid) {
switch (PR_htInst) {
case ADD_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
// Memory read request - Operand 1
MemAddr_t memRdAddr = SR_op1Addr + (P_vecIdx << 3);
ReadMem_op1Mem(memRdAddr, PR_htId);
HtContinue(ADD_LD2);
}
break;
case ADD_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
// Memory read request - Operand 2
MemAddr_t memRdAddr = SR_op2Addr + (P_vecIdx << 3);
ReadMem_op2Mem(memRdAddr, PR_htId);
ReadMemPause(ADD_PAUSE);
}
break;
case ADD_PAUSE: {
// Store op1 and op2 into private variables 'a' and 'b'.
P_a = S_op1Mem.read_mem();
P_b = S_op2Mem.read_mem();
// Mark inputs as valid, set htId
P_i_htId = PR_htId;
P_i_vld = true;
// Pause thread and wait for primitive to calculate the result...
// (will return to ADD_ST)
HtPause(ADD_ST);
}
break;
case ADD_ST: {
if (WriteMemBusy()) {
HtRetry();
break;
}
// Memory write request - Addition Result
MemAddr_t memWrAddr = SR_resAddr + (P_vecIdx << 3);
WriteMem(memWrAddr, S_resMem.read_mem());
WriteMemPause(ADD_RTN);
}
break;
case ADD_RTN: {
if (SendReturnBusy_add()) {
HtRetry();
break;
}
// Return Result from shared ram 'resMem'
SendReturn_add(S_resMem.read_mem());
}
break;
default:
assert(0);
}
}
// Temporary variables to use as outputs to the primitive
// (these are not saved between cycles)
uint64_t o_res;
ht_uint7 o_htId;
bool o_vld;
// use clocked primitive
add_5stage(P_a, P_b, P_i_htId, P_i_vld, o_res, o_htId, o_vld, add_prm_state1);
// Check for valid outputs from the primitive
if (o_vld) {
// Store Result into shared ram to be written to memory later
S_resMem.write_addr(o_htId);
S_resMem.write_mem(o_res);
// Wake up the thread (with corresponding htId)
HtResume(o_htId);
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
PW_test00_0_src_v0_data.write_addr(0, 7);
PW_test00_0_src_v0_data = ((int16_t)0x0013c9d0b2ab5b60LL);
P_test00_1_src_v0_data = ((ht_int53)0x0003070368ff74e0LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_src_v0_data(PR_memAddr + 0);
HtContinue(TEST00_ST1);
break;
}
case TEST00_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_1_src_v0_data(PR_memAddr + 64);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR_memAddr + 0);
HtContinue(TEST00_LD1);
break;
}
case TEST00_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_1_src_v0_data(PR_memAddr + 64);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if (SR_test00_0_dst_v0_data[1] != ((int16_t)0x0013c9d0b2ab5b60LL)) {
HtAssert(0, 0);
}
if (PR_test00_1_src_v0_data != ((ht_int53)0x0003070368ff74e0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersVadd::PersVadd()
{
if (PR_htValid) {
switch (PR_htInst) {
case VADD_RESET:
if (SR_msgDelay < 500 || SendHostMsgBusy()) {
S_msgDelay += 1;
HtRetry();
break;
}
SendHostMsg(VADD_TYPE_SIZE, (XDIM_LEN << 8) | TYPE_SIZE);
HtTerminate();
break;
case VADD_ENTER:
S_yIdx = 0;
S_yDimLen = PR_yDimLen;
S_xIdx = 0;
S_xDimLen = PR_xDimLen;
S_sum = 0;
S_addrA += PR_yAddrOff;
S_addrB += PR_yAddrOff;
S_addrC += PR_yAddrOff;
WriteStreamPause_C(VADD_OPEN);
break;
case VADD_OPEN:
// Open read stream A, once for each xDim to be processed
if (PR_yOpenAIdx < PR_yDimLen && !ReadStreamBusy_A()) {
ht_uint32 remLen = (ht_uint32)((PR_yDimLen - PR_yOpenAIdx) * PR_xDimLen);
ReadStreamOpen_A(SR_addrA, remLen > 0x3f ? (ht_uint6)0x3f : (ht_uint6)remLen, P_yOpenAIdx);
S_addrA += PR_xDimLen * TYPE_SIZE;
P_yOpenAIdx += 1;
}
// Open read stream B, once for each xDim to be processed
if (PR_yOpenBIdx < PR_yDimLen && !ReadStreamBusy_B()) {
ReadStreamOpen_B(SR_addrB, PR_xDimLen);
S_addrB += PR_xDimLen * TYPE_SIZE;
P_yOpenBIdx += 1;
}
// Open write stream, once for each xDim to be processed
if (PR_yOpenCIdx < SR_yDimLen && !WriteStreamBusy_C()) {
WriteStreamOpen_C(SR_addrC);
S_addrC += PR_xDimLen * TYPE_SIZE;
P_yOpenCIdx += 1;
}
if (PR_yOpenAIdx == PR_yDimLen && PR_yOpenBIdx == PR_yDimLen && PR_yOpenCIdx == PR_yDimLen)
WriteStreamPause_C(VADD_RETURN);
else
HtContinue(VADD_OPEN);
break;
case VADD_RETURN: {
BUSY_RETRY(SendReturnBusy_htmain());
SendReturn_htmain(S_sum);
}
break;
default:
assert(0);
}
}
if (SR_yIdx < SR_yDimLen &&
ReadStreamReady_A() &&
ReadStreamReady_B() &&
WriteStreamReady_C())
{
PersType_t a, b;
a = ReadStream_A();
b = ReadStream_B();
PersType_t c = a + b;
S_sum += (ht_uint32)c;
WriteStream_C(c);
assert_msg(SR_yIdx == ReadStreamTag_A(), "ReadStreamTag_A() error");
if (SR_xIdx + 1 < SR_xDimLen)
S_xIdx += 1;
else {
ReadStreamClose_A();
WriteStreamClose_C();
S_xIdx = 0;
S_yIdx += 1;
}
}
}
void CPersSub::PersSub() {
if (PR_htValid) {
switch (PR_htInst) {
case SUB_ENTRY: {
if (SendCallBusy_mult()) {
HtRetry();
break;
}
// Generate a seperate thread for each multiply operation within a matrix element
if (P_calcIdx < SR_comRC) {
SendCallFork_mult(SUB_JOIN, P_rowIdx, P_eleIdx, P_calcIdx);
HtContinue(SUB_ENTRY);
P_calcIdx += 1;
} else {
RecvReturnPause_mult(SUB_STORE);
}
}
break;
case SUB_JOIN: {
// Add resulting products into a sum variable
// The resulting element will be the sum of all multiply operations
P_eleSum += P_result;
RecvReturnJoin_mult();
}
break;
case SUB_STORE: {
if (WriteMemBusy()) {
HtRetry();
break;
}
// Memory write request - element
MemAddr_t memWrAddr = (ht_uint48)(SR_mcBase + ((P_rowIdx*SR_mcCol) << 3) + (P_eleIdx << 3));
WriteMem(memWrAddr, P_eleSum);
WriteMemPause(SUB_RTN);
}
break;
case SUB_RTN: {
if (SendReturnBusy_sub()) {
HtRetry();
break;
}
// Finished calculating matrix element
SendReturn_sub();
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
S_test00_0_src_u0_data.write_addr(0, 10);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[0][0].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[1][0].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[0][1].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[1][1].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[0][2].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_0_src_u0_data.write_mem().test00_0_src_u1_data[1][2].test00_0_src_v1_data = ((uint64_t)0x001169336de7cda0LL);
S_test00_1_src_v0_data = ((uint16_t)0x0003834a4c86abe0LL);
P_test00_2_src_u0_data[0].test00_2_src_u3_data.test00_2_src_v5_data = ((int16_t)0x0016951177fd7880LL);
GW_test00_3_src_v0_data.write_addr(1);
GW_test00_3_src_v0_data = ((int8_t)0x001e9fcdc4e5a160LL);
GW_test00_4_src_u0_data[0][0].test00_4_src_u2_data.test00_4_src_v6_data[1][0] = ((uint8_t)0x0017cdc6cc1a0560LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
S_test00_0_src_u0_data.read_addr(0, 10);
WriteMem_test00_0_src_u0_data_union(PR_memAddr + 0, SR_test00_0_src_u0_data.read_mem());
HtContinue(TEST00_ST1);
break;
}
case TEST00_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR_memAddr + 64, SR_test00_1_src_v0_data);
HtContinue(TEST00_ST2);
break;
}
case TEST00_ST2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_2_src_v5_data(PR_memAddr + 128, 0);
HtContinue(TEST00_ST3);
break;
}
case TEST00_ST3: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_3_src_v0_data(PR_memAddr + 192, 1, 1);
HtContinue(TEST00_ST4);
break;
}
case TEST00_ST4: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_4_src_v6_data(PR_memAddr + 256, 0, 0, 1, 0, 1);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_src_u0_data(PR_memAddr + 0, 0, 10, 1);
HtContinue(TEST00_LD1);
break;
}
case TEST00_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_1_dst_v0_data(PR_memAddr + 64, 5, 0, 1, 1);
P_test00_1_dst_v0_data_RdAddr1 = (ht_uint3)5;
HtContinue(TEST00_LD2);
break;
}
case TEST00_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_2_dst_v0_data(PR_memAddr + 128);
HtContinue(TEST00_LD3);
break;
}
case TEST00_LD3: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_3_dst_v0_data(PR_memAddr + 192);
HtContinue(TEST00_LD4);
break;
}
case TEST00_LD4: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_4_dst_v0_data(PR_memAddr + 256, 1, 2, 1);
P_test00_4_dst_v0_data_RdAddr1 = (ht_uint1)1;
P_test00_4_dst_v0_data_RdAddr2 = (ht_uint2)2;
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
SR_test00_0_src_u0_data.read_addr(0, 10);
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[0][0].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[1][0].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[0][1].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[1][1].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[0][2].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)S_test00_0_src_u0_data.read_mem().test00_0_src_u1_data[1][2].test00_0_src_v1_data != ((uint64_t)0x001169336de7cda0LL)) {
HtAssert(0, 0);
}
printf("EXP: 0x%04x\n", (uint16_t)0x0003834a4c86abe0LL);
printf("ACT: 0x%04x\n", (uint16_t)PR_test00_1_dst_v0_data[0][1]);
if ((uint16_t)PR_test00_1_dst_v0_data[0][1] != ((uint16_t)0x0003834a4c86abe0LL)) {
HtAssert(0, 0);
}
if ((int16_t)PR_test00_2_dst_v0_data[0] != ((int16_t)0x0016951177fd7880LL)) {
HtAssert(0, 0);
}
if ((int8_t)GR_test00_3_dst_v0_data[0] != ((int8_t)0x001e9fcdc4e5a160LL)) {
HtAssert(0, 0);
}
if ((uint8_t)GR_test00_4_dst_v0_data != ((uint8_t)0x0017cdc6cc1a0560LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersCtl::PersCtl()
{
if (PR_htValid) {
#ifndef _HTV
static const char *instructions[] = { "CTL_ENTRY", "CTL_RUN", "CTL_RTN" };
if (0 || (PR_htInst == CTL_ENTRY))
fprintf(stderr, "CTL: cmd=%s PR_cmd=%s S_rqAddr=%llx @ %lld\n",
instructions[(int)PR_htInst],
(PR_cmd == CMD_LD) ? "LD" : "ST",
(long long)S_rqAddr,
HT_CYCLE());
#endif
switch (PR_htInst) {
case CTL_ENTRY: {
P_rqIdx = 0;
P_rqCnt = 0;
HtContinue(CTL_RUN);
}
break;
case CTL_RUN: {
if (MemReadBusy() || MemWriteBusy()) {
HtRetry();
break;
}
// Memory request
MemAddr_t memAddr = S_rqAddr + (P_rqIdx << 3);
if (PR_cmd == CMD_LD)
MemRead_memRsp(memAddr);
else
MemWrite(memAddr, 0x600dbeef);
P_rqCnt = P_rqCnt + 1;
if ((P_rqIdx + 1) >= S_arrayLen)
P_rqIdx = 0;
else
P_rqIdx = P_rqIdx + 1;
if (P_rqCnt >= P_numReqs)
HtContinue(CTL_RTN);
else
HtContinue(CTL_RUN);
}
break;
case CTL_RTN: {
if (ReturnBusy_htmain()) {
HtRetry();
break;
}
Return_htmain(P_rqCnt);
}
break;
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST00_ENTRY: {
break;
}
case TEST00_WR: {
break;
}
case TEST00_ST0: {
break;
}
case TEST00_ST1: {
break;
}
case TEST00_ST2: {
break;
}
case TEST00_ST3: {
break;
}
case TEST00_ST4: {
break;
}
case TEST00_LD0: {
break;
}
case TEST00_LD1: {
break;
}
case TEST00_LD2: {
break;
}
case TEST00_LD3: {
break;
}
case TEST00_LD4: {
break;
}
case TEST00_CHK: {
break;
}
case TEST00_RTN: {
break;
}
default:
assert(0);
}
}
if (PR3_htValid) {
switch (PR3_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR);
break;
}
case TEST00_WR: {
GW3_test00_0_src_v0_data = ((int16_t)0x00192aa94393dec0LL);
GW3_test00_1_src_v0_data[0] = ((uint32_t)0x00111ffb66693520LL);
GW3_test00_2_src_v0_data.write_addr(3);
GW3_test00_2_src_v0_data = ((uint32_t)0x001d7f229c1c49a0LL);
GW3_test00_3_src_v0_data[0][0].write_addr(0, 0);
GW3_test00_3_src_v0_data[0][0] = ((uint16_t)0x000cec97f4c84740LL);
GW3_test00_4_src_v0_data.write_addr(1, 9);
GW3_test00_4_src_v0_data = ((uint64_t)0x000beba9f75cc5c0LL);
P3_test00_2_src_v0_data_RdAddr1 = (ht_uint3)3;
P3_test00_3_src_v0_data_RdAddr1 = (ht_uint1)0;
P3_test00_3_src_v0_data_RdAddr2 = (ht_uint2)0;
P3_test00_4_src_v0_data_RdAddr1 = (ht_uint1)1;
P3_test00_4_src_v0_data_RdAddr2 = (ht_uint4)9;
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_int16_t(PR3_memAddr + 0, GR3_test00_0_src_v0_data);
HtContinue(TEST00_ST1);
break;
}
case TEST00_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_1_src_v0_data(PR3_memAddr + 64);
HtContinue(TEST00_ST2);
break;
}
case TEST00_ST2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint32_t(PR3_memAddr + 128, GR3_test00_2_src_v0_data);
HtContinue(TEST00_ST3);
break;
}
case TEST00_ST3: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR3_memAddr + 192, GR3_test00_3_src_v0_data[0][0]);
HtContinue(TEST00_ST4);
break;
}
case TEST00_ST4: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint64_t(PR3_memAddr + 256, GR3_test00_4_src_v0_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_v0_data(PR3_memAddr + 0);
HtContinue(TEST00_LD1);
break;
}
case TEST00_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_1_dst_v1_data(PR3_memAddr + 64, 0);
HtContinue(TEST00_LD2);
break;
}
case TEST00_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_2_dst_v0_data(PR3_memAddr + 128, 1, 1);
HtContinue(TEST00_LD3);
break;
}
case TEST00_LD3: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_3_dst_v1_data(PR3_memAddr + 192, 12, 0, 0, 0, 0, 1);
P3_test00_3_dst_s0_data_RdAddr1 = (ht_uint4)12;
P3_test00_3_dst_s0_data_RdAddr2 = (ht_uint1)0;
HtContinue(TEST00_LD4);
break;
}
case TEST00_LD4: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_4_dst_v0_data(PR3_memAddr + 256, 1, 1, 1, 2, 1, 1);
P3_test00_4_dst_s0_data_RdAddr1 = (ht_uint1)1;
P3_test00_4_dst_s0_data_RdAddr2 = (ht_uint1)1;
ReadMemPause(TEST00_CHK);
break;
}
case TEST00_CHK: {
if ((int16_t)P3_test00_0_dst_s0_data.test00_0_dst_v0_data != ((int16_t)0x00192aa94393dec0LL)) {
HtAssert(0, 0);
}
if ((uint32_t)SR_test00_1_dst_u0_data[0].test00_1_dst_v1_data != ((uint32_t)0x00111ffb66693520LL)) {
HtAssert(0, 0);
}
if ((uint32_t)PR3_test00_2_dst_v0_data[1] != ((uint32_t)0x001d7f229c1c49a0LL)) {
HtAssert(0, 0);
}
if ((uint16_t)GR3_test00_3_dst_s0_data[0].test00_3_dst_v1_data[0][0] != ((uint16_t)0x000cec97f4c84740LL)) {
HtAssert(0, 0);
}
if ((uint64_t)PR3_test00_4_dst_s0_data[1].test00_4_dst_v0_data[2][1] != ((uint64_t)0x000beba9f75cc5c0LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void
CPersInc7::PersInc7()
{
if (PR_htValid) {
//sc_uint<INC_WR_RSP_GRP_ID_W> wrRspGrpId = (sc_uint<INC_WR_RSP_GRP_ID_W>)((P_htId << 2) | (P_htId & 3));
//static int cnt = 0;
//if (++cnt == 151)
// bool stop = true;
//printf("%d - HtId %d: inst %d\n", cnt, (int)PR_htId, (int)PR_htInst);
switch (PR_htInst) {
case INC7_INIT:
{
P_loopIdx = 0;
P_rdGrpId = PR_htId ^ 0x5;
//if (m_htIdPool.empty())
// wait until all threads have started
HtContinue(INC7_READ);
//else
// HtContinue(INC7_INIT);
}
break;
case INC7_READ:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = SR_arrayAddr + ((P_loopBase + P_loopIdx) << 3);
Inc7Ptr_t arrayMemWrPtr = (PR_htId << 7) | P_loopIdx;
// Issue read request to memory
ReadMem_arrayMem7(PR_rdGrpId, memRdAddr, arrayMemWrPtr);
bool bLast = P_loopIdx == P_elemCnt - 1;
if (bLast) {
P_loopIdx = 0;
ReadMemPause(PR_rdGrpId, INC7_WRITE);
} else {
P_loopIdx += 1;
HtContinue(INC7_READ);
}
// Set address for reading memory response data
P_arrayMemRdPtr = (PR_htId << 7) | P_loopIdx;
}
break;
case INC7_WRITE:
{
//if (WriteMemBusy(rspGrpId)) {
if (WriteMemBusy()) {
//if (WriteMemBusy(wrRspGrpId)) {
HtRetry();
break;
}
// Increment memory data
uint64_t memWrData = GR_arrayMem7.data + 1;
// Calculate memory write address
MemAddr_t memWrAddr = SR_arrayAddr + ((P_loopBase + P_loopIdx) << 3);
// Issue write memory request
//WriteMem(wrRspGrpId, memWrAddr, memWrData);
WriteMem(memWrAddr, memWrData);
bool bLast = P_loopIdx == P_elemCnt - 1;
if (bLast) {
P_loopIdx = 0;
//WriteMemPause(wrRspGrpId, INC7_RTN);
WriteMemPause(INC7_RTN);
//HtPause();
} else {
P_loopIdx += 1;
HtContinue(INC7_WRITE);
}
// Set address for reading memory response data
P_arrayMemRdPtr = (PR_htId << 7) | P_loopIdx;
}
break;
case INC7_RTN:
{
if (SendReturnBusy_inc7()) {
HtRetry();
break;
}
SendReturn_inc7(P_elemCnt);
break;
}
default:
assert(0);
}
}
}
void CPersF8::PersF8()
{
if (PR1_htValid) {
switch (PR1_htInst) {
case F8_ENTRY:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
ht_uint2 rdGrpId = 0;
S_rslt64[rdGrpId] = 0;
ReadMem_func64(rdGrpId, PR1_addr, 0x15, 256);
ReadMemPause(rdGrpId, F8_RD32);
break;
}
case F8_RD32:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
HtAssert(SR_rslt64[0] == 9574400, 0);
ht_uint2 rdGrpId = 1;
S_rslt32[rdGrpId] = 0;
ReadMem_func32(rdGrpId, PR1_addr + 256 * 8, 0x75, 64);
ReadMemPause(rdGrpId, F8_RD16);
break;
}
case F8_RD16:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
HtAssert(SR_rslt32[1] == 341376, 0);
ht_uint2 rdGrpId = 2;
ReadMem_func16(rdGrpId, PR1_addr, 0x9);
ReadMemPause(rdGrpId, F8_RD64DLY);
break;
}
case F8_RD64DLY:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
ht_uint2 rdGrpId = 3;
S_rslt64Dly[rdGrpId] = 0;
ReadMem_func64Dly(rdGrpId, PR1_addr, 0x19, 32);
ReadMemPause(rdGrpId, F8_RD64GBL);
break;
}
case F8_RD64GBL:
{
if (ReadMemBusy()) {
HtRetry();
break;
}
HtAssert(SR_rslt64Dly[3] == 71424, 0);
ht_uint2 rdGrpId = 3;
ReadMem_gbl(rdGrpId, PR1_addr + 8);
P1_gvAddr = 12;
ReadMemPause(rdGrpId, F8_RETURN);
break;
}
case F8_RETURN: {
if (SendReturnBusy_f8()) {
HtRetry();
break;
}
HtAssert(GR1_gbl.u64 == 124, 0);
SendReturn_f8();
break;
}
default:
assert(0);
}
}
T1_rdRspData = 0;
S_rslt64Dly[3] += T2_rdRspData;
}
void CPersTest05::PersTest05() {
if (PR1_htValid) {
switch (PR1_htInst) {
case TEST05_ENTRY: {
HtContinue(TEST05_WR);
break;
}
case TEST05_WR: {
GW1_test05_1_src_v0_data.write_addr(1, 2);
GW1_test05_1_src_v0_data = ((uint32_t)0x000e0ee0743246a0LL);
S_test05_2_src_v0_data[1][0] = ((uint64_t)0x0016f0f7024f88c0LL);
S_test05_3_dst_s0_data[1].write_addr(1);
S_test05_3_dst_s0_data[1].write_mem().test05_3_dst_v0_data = ((int8_t)0x000fe190cc1c5d20LL);
HtContinue(TEST05_ST0);
break;
}
case TEST05_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_int16_t(PR1_memAddr + 0, PR1_test05_0_src_v0_data[2]);
HtContinue(TEST05_ST1);
break;
}
case TEST05_ST1: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test05_1_src_v0_data(PR1_memAddr + 64, 1, 2, 1);
HtContinue(TEST05_ST2);
break;
}
case TEST05_ST2: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test05_2_src_v0_data(PR1_memAddr + 128, 1, 0, 1);
HtContinue(TEST05_ST3);
break;
}
case TEST05_ST3: {
if (WriteMemBusy()) {
HtRetry();
break;
}
SR_test05_3_dst_s0_data[1].read_addr(1);
WriteMem_test05_3_dst_s0_data_struct(PR1_memAddr + 192, SR_test05_3_dst_s0_data[1].read_mem());
WriteMemPause(TEST05_LD0);
break;
}
case TEST05_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test05_0_dst_v0_data(PR1_memAddr + 0, 2, 0, 1);
HtContinue(TEST05_LD1);
break;
}
case TEST05_LD1: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test05_1_src_v0_data(PR1_memAddr + 64, 1, 2, 1);
HtContinue(TEST05_LD2);
break;
}
case TEST05_LD2: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test05_2_dst_v0_data(PR1_memAddr + 128, 2, 14, 0, 0, 1);
HtContinue(TEST05_LD3);
break;
}
case TEST05_LD3: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test05_3_dst_s0_data(PR1_memAddr + 192, 1, 1, 1);
ReadMemPause(TEST05_CHK);
break;
}
case TEST05_CHK: {
if ((int16_t)GR1_test05_0_dst_u0_data[2].test05_0_dst_v0_data[0][1] != ((int16_t)0x0004b4ff2aff2220LL)) {
HtAssert(0, 0);
}
if ((uint32_t)GR1_test05_1_src_v0_data != ((uint32_t)0x000e0ee0743246a0LL)) {
HtAssert(0, 0);
}
if ((uint64_t)GR1_test05_2_dst_v0_data[0][0] != ((uint64_t)0x0016f0f7024f88c0LL)) {
HtAssert(0, 0);
}
SR_test05_3_dst_s0_data[1].read_addr(1);
if ((int8_t)SR_test05_3_dst_s0_data[1].read_mem().test05_3_dst_v0_data != ((int8_t)0x000fe190cc1c5d20LL)) {
HtAssert(0, 0);
}
HtContinue(TEST05_RTN);
break;
}
case TEST05_RTN: {
if (SendReturnBusy_test05()) {
HtRetry();
break;
}
SendReturn_test05();
break;
}
default:
assert(0);
}
}
if (PR2_htValid) {
switch (PR2_htInst) {
case TEST05_ENTRY: {
break;
}
case TEST05_WR: {
PW2_test05_0_src_v0_data[2].write_addr(3, 0);
PW2_test05_0_src_v0_data[2] = ((int16_t)0x0004b4ff2aff2220LL);
P2_test05_0_src_v0_data_RdAddr1 = (ht_uint2)3;
P2_test05_0_src_v0_data_RdAddr2 = (ht_uint1)0;
break;
}
case TEST05_ST0: {
break;
}
case TEST05_ST1: {
break;
}
case TEST05_ST2: {
break;
}
case TEST05_ST3: {
break;
}
case TEST05_LD0: {
break;
}
case TEST05_LD1: {
P2_test05_1_src_v0_data_RdAddr1 = (ht_uint1)1;
P2_test05_1_src_v0_data_RdAddr2 = (ht_uint2)2;
break;
}
case TEST05_LD2: {
P2_test05_2_dst_v0_data_RdAddr1 = (ht_uint4)2;
P2_test05_2_dst_v0_data_RdAddr2 = (ht_uint4)14;
break;
}
case TEST05_LD3: {
break;
}
case TEST05_CHK: {
break;
}
case TEST05_RTN: {
break;
}
default:
assert(0);
}
}
}
void CPersTest00::PersTest00() {
if (PR_htValid) {
switch (PR_htInst) {
case TEST00_ENTRY: {
HtContinue(TEST00_WR0);
break;
}
case TEST00_WR0: {
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data = ((int32_t)0x0002daa2633de3e0LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][0] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][1] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][2] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][3] = ((int32_t)0x0000ba052338b540LL);
S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v3_data = ((uint32_t)0x00194f52bcc93520LL);
HtContinue(TEST00_ST0);
break;
}
case TEST00_ST0: {
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_test00_0_dst_s2_data_struct(PR_memAddr + 0, SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data);
WriteMemPause(TEST00_LD0);
break;
}
case TEST00_LD0: {
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_test00_0_dst_s2_data(PR_memAddr + 0);
ReadMemPause(TEST00_CHK0);
break;
}
case TEST00_CHK0: {
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data != ((int32_t)0x0002daa2633de3e0LL)) {
printf("EXP: 0x%08x\n", (int32_t)0x0002daa2633de3e0LL);
printf("ACT: 0x%08x\n\n", (int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v1_data);
HtAssert(0, 0);
}
if ((int32_t)SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][0] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][1] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)SR_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][2] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((int32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v2_data[0][3] != ((int32_t)0x0000ba052338b540LL)) {
HtAssert(0, 0);
}
if ((uint32_t)S_test00_0_dst_s0_data.test00_0_dst_s1_data.test00_0_dst_s2_data.test00_0_dst_v3_data != ((uint32_t)0x00194f52bcc93520LL)) {
HtAssert(0, 0);
}
HtContinue(TEST00_RTN);
break;
}
case TEST00_RTN: {
if (SendReturnBusy_test00()) {
HtRetry();
break;
}
SendReturn_test00();
break;
}
default:
assert(0);
}
}
}
void CPersGv11::PersGv11()
{
if (PR_htValid) {
switch (PR_htInst) {
case GV11_ENTRY:
if (SendCallBusy_gv12a()) {
HtRetry();
break;
}
GW_Gv12a.data = 0x1234;
SendCall_gv12a(GV11_gv12b, PR_addr);
break;
case GV11_gv12b:
if (SendCallBusy_gv12b()) {
HtRetry();
break;
}
P_addr1 = 5;
GW_Gv12b.write_addr(P_addr1);
GW_Gv12b.data = 0x2345;
SendCall_gv12b(GV11_gv12c_WR, P_addr1);
break;
case GV11_gv12c_WR:
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR_addr, 0x3456);
WriteMemPause(GV11_gv12c_RD);
break;
case GV11_gv12c_RD:
if (ReadMemBusy()) {
HtRetry();
break;
}
ReadMem_Gv12c(PR_addr);
ReadMemPause(GV11_gv12c);
break;
case GV11_gv12c:
if (SendCallBusy_gv12c()) {
HtRetry();
break;
}
SendCall_gv12c(GV11_gv12d_WR, PR_addr);
break;
case GV11_gv12d_WR:
if (WriteMemBusy()) {
HtRetry();
break;
}
WriteMem_uint16_t(PR_addr, 0x4567);
WriteMemPause(GV11_gv12d_RD);
break;
case GV11_gv12d_RD:
if (ReadMemBusy()) {
HtRetry();
break;
}
P_addr1 = 6;
ReadMem_Gv12d(PR_addr, P_addr1, 1);
ReadMemPause(GV11_gv12d);
break;
case GV11_gv12d:
if (SendCallBusy_gv12d()) {
HtRetry();
break;
}
SendCall_gv12d(GV11_RETURN, PR_addr1);
break;
case GV11_RETURN:
if (SendReturnBusy_gv11()) {
HtRetry();
break;
}
SendReturn_gv11();
break;
default:
assert(0);
}
}
}
void
CPersSch::PersSch()
{
//sch_thr_idx_t wcid = (sch_thr_idx_t)RecvMsg_schPush().m_connId;
// UDP must go through the same queue based on pConn index
uint16_t nxtCid = RecvMsg_schPush().m_connId;
sch_thr_idx_t wcid = cid2que(nxtCid);
sch_que_idx_t wadr = S_queWrIdx[wcid];
m_queDat.write_addr(wcid, wadr);
if (!RecvMsgBusy_schPush()) {
m_queDat.write_mem(RecvMsg_schPush());
S_queWrIdx[wcid] += 1;
}
//
// Stage 1
//
sch_que_idx_t radr = S_queRdIdx[PR1_htId];
m_queDat.read_addr(PR1_htId, radr);
T1_bEmpty = SR_queWrIdx[PR1_htId] == SR_queRdIdx[PR1_htId];
//
// Stage 2
//
if (PR2_htValid) {
switch (PR2_htInst) {
case SCH_SPIN: {
if (SendCallBusy_ProcessPkt()
|| SendMsgBusy_schPop()
|| TR2_bEmpty) {
HtRetry();
break;
}
uint16_t cid = S_queDat.read_mem().m_connId;
conn_addr_t cidAddr = cid2addr(cid);
#ifndef _HTV
extern FILE *tfp;
if (tfp)
fprintf(tfp, "SCH: Calling Pkt cid=0x%04x blkIdx=%d @ %lld\n",
(int)cid, (int)S_queDat.read_mem().m_info.m_blkIndex,
(long long)sc_time_stamp().value() / 10000);
#endif
SendCall_ProcessPkt(SCH_RETURN,
S_queDat.read_mem().m_info,
cid, cidAddr);
S_queRdIdx[PR2_htId] += 1;
SendMsg_schPop(PR2_htId);
}
break;
case SCH_RETURN: {
HtContinue(SCH_SPIN);
}
break;
default:
if (SendReturnBusy_sch()) {
HtRetry();
break;
}
SendReturn_sch();
assert(0);
}
}
if (GR_htReset) {
for (int i=0; i<16; i++) {
S_queWrIdx[i] = 0;
S_queRdIdx[i] = 0;
}
}
}
void CPersWr3::PersWr3()
{
if (PR_htValid) {
switch (PR_htInst) {
case WR3_INIT:
{
P_loopCnt = 0;
P_err = 0;
P_pauseLoopCnt = 0;
HtContinue(WR3_WRITE1);
}
break;
case WR3_WRITE1:
{
if (WriteMemBusy() || SendReturnBusy_wr3()) {
HtRetry();
break;
}
// Check if end of loop
if (P_loopCnt == PAUSE_LOOP_CNT || P_err) {
// Return to host interface
SendReturn_wr3(P_err);
} else {
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + ((P_loopCnt & 0xf) << 3);
// Issue read request to memory
WriteMem(PR_wrGrpId, memRdAddr, (P_loopCnt & 0xf));
// Set address for reading memory response data
HtContinue(WR3_WRITE2);
}
}
break;
case WR3_WRITE2:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 1) & 0xf) << 3);
// Issue read request to memory
WriteMem(PR_wrGrpId, memRdAddr, ((P_loopCnt + 1) & 0xf));
HtContinue(WR3_WRITE3);
}
break;
case WR3_WRITE3:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 2) & 0xf) << 3);
// Issue read request to memory
WriteMem(PR_wrGrpId, memRdAddr, ((P_loopCnt + 2) & 0xf));
HtContinue(WR3_WRITE4);
}
break;
case WR3_WRITE4:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// Calculate memory read address
MemAddr_t memRdAddr = P_arrayAddr + (((P_loopCnt + 3) & 0xf) << 3);
// Issue read request to memory
WriteMem(PR_wrGrpId, memRdAddr, ((P_loopCnt + 3) & 0xf));
HtContinue(WR3_LOOP);
}
break;
case WR3_LOOP:
{
if (WriteMemBusy()) {
HtRetry();
break;
}
// wait a few instructions for last response to line up with call to ReadMemPause
if (P_pauseLoopCnt == 2) {
P_pauseLoopCnt = 0;
P_loopCnt += 1;
WriteMemPause(PR_wrGrpId, WR3_WRITE1);
} else {
P_pauseLoopCnt += 1;
HtContinue(WR3_LOOP);
}
}
break;
default:
assert(0);
}
}
#ifndef _HTV
if (r_m1_wrRspRdy) {
#if (WR3_WR_GRP_W == 0)
if (!r_wrGrpRsmWait)
printf("-");
else if (r_wrGrpRspCnt == 1)
printf("1");
else
printf("+");
#else
#if (WR3_WR_GRP_W <= 2)
if (r_wrGrpState[r_m1_wrGrpId].m_pause)
printf("-");
else if (r_wrGrpState[r_m1_wrGrpId].m_cnt == 1)
printf("3");
else
printf("+");
#else
{
m_wrGrpReqState1.read_addr(r_m1_wrGrpId);
m_wrGrpRspState0.read_addr(r_m1_wrGrpId);
CWrGrpRspState c_m2_wrGrpRspState = m_wrGrpRspState0.read_mem();
CWrGrpReqState c_m2_wrGrpReqState = m_wrGrpReqState1.read_mem();
if (c_m2_wrGrpRspState.m_pause == c_m2_wrGrpReqState.m_pause)
printf("-");
else if (c_m2_wrGrpReqState.m_cnt - c_m2_wrGrpRspState.m_cnt == 1)
printf("3");
else
printf("+");
}
#endif
#endif
}
#endif
}
