/* SCL Divisor = 8 * (CLKDIVL + CLKDIVH) * SCL = i2c_rate/ SCLK Divisor */ static void rk30_i2c_set_clk(struct rk30_i2c *i2c, unsigned long scl_rate) { unsigned long i2c_rate = clk_get_rate(i2c->clk); unsigned int div, divl, divh; if((scl_rate == i2c->scl_rate) && (i2c_rate == i2c->i2c_rate)) return; i2c->i2c_rate = i2c_rate; i2c->scl_rate = scl_rate; div = rk30_ceil(i2c_rate, scl_rate * 8); divh = divl = rk30_ceil(div, 2); i2c_writel(I2C_CLKDIV_VAL(divl, divh), i2c->regs + I2C_CLKDIV); i2c_dbg(i2c->dev, "set clk(I2C_CLKDIV: 0x%08x)\n", i2c_readl(i2c->regs + I2C_CLKDIV)); return; }
void __sramfunc sram_i2c_init() { unsigned int div, divl, divh; //enable cru_clkgate8 clock data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8))); cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1)); data[2] = readl_relaxed(RK30_GRF_BASE + GRF_GPIO_IOMUX); writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK30_GRF_BASE + GRF_GPIO_IOMUX); div = 0x1e; divh = divl = 0xf; writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV); data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV); }
/* * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1) * SCL = PCLK / SCLK Divisor * i2c_rate = PCLK */ static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate) { uint32_t i2c_rate; int div, divl, divh; /* First get i2c rate from pclk */ i2c_rate = clk_get_rate(&i2c->clk); div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; divh = 0; divl = 0; if (div >= 0) rk_i2c_get_div(div, &divh, &divl); writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv); debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate, scl_rate); debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl); debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); }
void __sramfunc sram_i2c_init(void) { unsigned int div, divl, divh; //enable cru_clkgate8 clock data[1] = cru_readl(CLK_GATE_CLKID_CONS(CLK_GATE_CLKID(8))); #if defined (CONFIG_MACH_RK2928_SDK) || defined( CONFIG_ARCH_RK3026_TB)||defined(CONFIG_ARCH_RK3028A_TB) cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C1)|CLK_UN_GATE(CLK_GATE_PCLK_I2C1), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C1)); #else cru_writel(CLK_GATE_W_MSK(CLK_GATE_PCLK_I2C0)|CLK_UN_GATE(CLK_GATE_PCLK_I2C0), CLK_GATE_CLKID_CONS(CLK_GATE_PCLK_I2C0)); #endif data[2] = readl_relaxed(RK2928_GRF_BASE + GRF_GPIO_IOMUX); writel_relaxed(data[2]| I2C_GRF_GPIO_IOMUX, RK2928_GRF_BASE + GRF_GPIO_IOMUX); div = 0x1e; divh = divl = 0xf; writel_relaxed(I2C_CLKDIV_VAL(divl, divh), SRAM_I2C_ADDRBASE + I2C_CLKDIV); data[3] = readl_relaxed(SRAM_I2C_ADDRBASE + I2C_CLKDIV); }