/**
* Main entry point for the AMD_INIT_ENV function.
*
* This entry point is responsible for copying the heap contents from the
* temp RAM area to main memory.
*
* @param[in,out] EnvParams Required input parameters for the AMD_INIT_ENV
* entry point.
*
* @return Aggregated status across all internal AMD env calls invoked.
*
*/
AGESA_STATUS
AmdInitEnv (
IN OUT AMD_ENV_PARAMS *EnvParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitEnvStatus;
AGESA_TESTPOINT (TpIfAmdInitEnvEntry, &EnvParams->StdHeader);
ASSERT (EnvParams != NULL);
AmdInitEnvStatus = AGESA_SUCCESS;
//Copy Temp Ram heap content to Main Ram
AgesaStatus = CopyHeapToMainRamAtPost (&(EnvParams->StdHeader));
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
EnvParams->StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
EnvParams->StdHeader.HeapBasePtr = HeapGetBaseAddress (&EnvParams->StdHeader);
// Any heap allocate/deallocate/locate buffer should be used after heap is rebuilt from here.
// After persistent heaps are transferred and rebuilt, HeapLocateBuffer can start to be used in IDS hook.
//Heap have been relocated, so Debug Print need be init again to get new address
IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_INIT (&EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer End\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitEnv: Start\n\n");
IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &EnvParams->PlatformConfig, &(EnvParams->StdHeader));
IDS_OPTION_HOOK (IDS_BEFORE_PCI_INIT, EnvParams, &(EnvParams->StdHeader));
AgesaStatus = S3ScriptInit (&EnvParams->StdHeader);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_BEGININITENV, &EnvParams->StdHeader);
AgesaStatus = BldoptFchFunction.InitEnv (EnvParams);
AmdInitEnvStatus = (AgesaStatus > AmdInitEnvStatus) ? AgesaStatus : AmdInitEnvStatus;
IDS_PERF_TIMESTAMP (TP_ENDINITENV, &EnvParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATENV, &EnvParams->StdHeader);
AgesaStatus = GnbInitAtEnv (EnvParams);
if (AgesaStatus > AmdInitEnvStatus) {
AmdInitEnvStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATENV, &EnvParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitEnvExit, &EnvParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitEnv: End\n");
IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITENV, &EnvParams->StdHeader);
IDS_HDT_CONSOLE_FLUSH_BUFFER (&EnvParams->StdHeader);
return AmdInitEnvStatus;
}
/**
* Main entry point for the AMD_INIT_MID function.
*
* This entry point is responsible for performing any necessary functions needed
* after PCI bus enumeration and just before control is passed to the video option ROM.
*
* @param[in,out] MidParams Required input parameters for the AMD_INIT_MID
* entry point.
*
* @return Aggregated status across all internal AMD mid calls invoked.
*
*/
AGESA_STATUS
AmdInitMid (
IN OUT AMD_MID_PARAMS *MidParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS CalledStatus;
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n");
AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader);
IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
AgesaStatus = AGESA_SUCCESS;
ASSERT (MidParams != NULL);
IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n");
CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n");
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
CalledStatus = GnbInitAtMid (MidParams);
if (CalledStatus > AgesaStatus) {
AgesaStatus = CalledStatus;
}
IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader);
IDS_PERF_TIME_MEASURE (&MidParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n");
IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader);
return AgesaStatus;
}
/**
* Main entry point for the AMD_INIT_POST function.
*
* This entry point is responsible for initializing all system memory,
* gathering important data out of the pre-memory cache storage into a
* temporary holding buffer in main memory. After that APs will be
* shutdown in preparation for the host environment to take control.
* Note: pre-memory stack will be disabled also.
*
* @param[in,out] PostParams Required input parameters for the AMD_INIT_POST
* entry point.
*
* @return Aggregated status across all internal AMD POST calls invoked.
*
*/
AGESA_STATUS
AmdInitPost (
IN OUT AMD_POST_PARAMS *PostParams
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS AmdInitPostStatus;
WARM_RESET_REQUEST Request;
UINT8 PrevRequestBit;
UINT8 PrevStateBits;
IDS_PERF_TIMESTAMP (TP_BEGINPROCAMDINITPOST, &PostParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitPostEntry, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitPost: Start\n\n");
ASSERT (PostParams != NULL);
AmdInitPostStatus = AGESA_SUCCESS;
PrevRequestBit = FALSE;
PrevStateBits = WR_STATE_COLD;
IDS_OPTION_HOOK (IDS_INIT_POST_BEFORE, PostParams, &PostParams->StdHeader);
// If a previously requested warm reset cannot be triggered in the
// current stage, store the previous state of request and reset the
// request struct to the current post stage
GetWarmResetFlag (&PostParams->StdHeader, &Request);
if (Request.RequestBit == TRUE) {
if (Request.StateBits >= Request.PostStage) {
PrevRequestBit = Request.RequestBit;
PrevStateBits = Request.StateBits;
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
}
}
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATPOST, &PostParams->StdHeader);
AgesaStatus = GnbInitAtPost (PostParams);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATPOST, &PostParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_BEGINAMDMEMAUTO, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: Start\n");
PostParams->MemConfig.MemData->StdHeader = PostParams->StdHeader;
AgesaStatus = AmdMemAuto (PostParams->MemConfig.MemData);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdMemAuto: End\n");
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDAMDMEMAUTO, &PostParams->StdHeader);
if (AgesaStatus != AGESA_FATAL) {
// Check BIST status
AgesaStatus = CheckBistStatus (&PostParams->StdHeader);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
//
// P-State data gathered, then, Relinquish APs
//
IDS_PERF_TIMESTAMP (TP_BEGINAMDCPUPOST, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: Start\n");
AgesaStatus = AmdCpuPost (&PostParams->StdHeader, &PostParams->PlatformConfig);
IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuPost: End\n");
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDAMDCPUPOST, &PostParams->StdHeader);
// Warm Reset
GetWarmResetFlag (&PostParams->StdHeader, &Request);
// If a warm reset is requested in the current post stage, trigger the
// warm reset and ignore the previous request
if (Request.RequestBit == TRUE) {
if (Request.StateBits < Request.PostStage) {
AgesaDoReset (WARM_RESET_WHENEVER, &PostParams->StdHeader);
}
} else {
// Otherwise, if there's a previous request, restore it
// so that the subsequent post stage can trigger the warm reset
if (PrevRequestBit == TRUE) {
Request.RequestBit = PrevRequestBit;
Request.StateBits = PrevStateBits;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
}
}
IDS_PERF_TIMESTAMP (TP_BEGINGNBINITATPOSTAFTERDRAM, &PostParams->StdHeader);
AgesaStatus = GnbInitAtPostAfterDram (PostParams);
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
IDS_PERF_TIMESTAMP (TP_ENDGNBINITATPOSTAFTERDRAM, &PostParams->StdHeader);
IDS_OPTION_HOOK (IDS_INIT_POST_AFTER, PostParams, &PostParams->StdHeader);
AGESA_TESTPOINT (TpIfAmdInitPostExit, &PostParams->StdHeader);
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitPost: End\n\n");
IDS_HDT_CONSOLE (MAIN_FLOW, "Heap transfer Start ...\n\n");
//For Heap will be relocate to new address in next stage, flush out debug print buffer if needed
IDS_HDT_CONSOLE_FLUSH_BUFFER (&PostParams->StdHeader);
// WARNING: IDT will be moved from local cache to temp memory, so restore IDTR for BSP here
IDS_EXCEPTION_TRAP (IDS_IDT_RESTORE_IDTR_FOR_BSC, NULL, &PostParams->StdHeader);
IDS_PERF_TIMESTAMP (TP_ENDPROCAMDINITPOST, &PostParams->StdHeader);
// Copies BSP heap content to RAM, and it should be at the end of AmdInitPost
AgesaStatus = CopyHeapToTempRamAtPost (&(PostParams->StdHeader));
if (AgesaStatus > AmdInitPostStatus) {
AmdInitPostStatus = AgesaStatus;
}
PostParams->StdHeader.HeapStatus = HEAP_TEMP_MEM;
}
// Check for Cache As Ram Corruption
IDS_CAR_CORRUPTION_CHECK (&PostParams->StdHeader);
// At the end of AmdInitPost, set StateBits to POST to allow any warm reset that occurs outside
// of AGESA to be recognized by IsWarmReset()
GetWarmResetFlag (&PostParams->StdHeader, &Request);
Request.StateBits = Request.PostStage;
SetWarmResetFlag (&PostParams->StdHeader, &Request);
return AmdInitPostStatus;
}