MX35_PAD_RESERVE193 = 474,
MX35_PAD_RESERVE194 = 475,
MX35_PAD_RESERVE195 = 476,
MX35_PAD_RESERVE196 = 477,
MX35_PAD_RESERVE197 = 478,
MX35_PAD_RESERVE198 = 479,
MX35_PAD_RESERVE199 = 480,
MX35_PAD_RESERVE200 = 481,
MX35_PAD_RESERVE201 = 482,
MX35_PAD_EXT_ARMCLK = 483,
MX35_PAD_TEST_MODE = 484,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX35_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX35_PAD_CAPTURE),
IMX_PINCTRL_PIN(MX35_PAD_COMPARE),
IMX_PINCTRL_PIN(MX35_PAD_WDOG_RST),
IMX_PINCTRL_PIN(MX35_PAD_GPIO1_0),
IMX_PINCTRL_PIN(MX35_PAD_GPIO1_1),
IMX_PINCTRL_PIN(MX35_PAD_GPIO2_0),
IMX_PINCTRL_PIN(MX35_PAD_GPIO3_0),
IMX_PINCTRL_PIN(MX35_PAD_CLKO),
IMX_PINCTRL_PIN(MX35_PAD_VSTBY),
IMX_PINCTRL_PIN(MX35_PAD_A0),
IMX_PINCTRL_PIN(MX35_PAD_A1),
IMX_PINCTRL_PIN(MX35_PAD_A2),
IMX_PINCTRL_PIN(MX35_PAD_A3),
IMX_PINCTRL_PIN(MX35_PAD_A4),
IMX_PINCTRL_PIN(MX35_PAD_A5),
MX50_PAD_EIM_CS1 = 168,
MX50_PAD_EIM_CS0 = 169,
MX50_PAD_EIM_EB0 = 170,
MX50_PAD_EIM_EB1 = 171,
MX50_PAD_EIM_WAIT = 172,
MX50_PAD_EIM_BCLK = 173,
MX50_PAD_EIM_RDY = 174,
MX50_PAD_EIM_OE = 175,
MX50_PAD_EIM_RW = 176,
MX50_PAD_EIM_LBA = 177,
MX50_PAD_EIM_CRE = 178,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
VF610_PAD_PTE19 = 124,
VF610_PAD_PTE20 = 125,
VF610_PAD_PTE21 = 126,
VF610_PAD_PTE22 = 127,
VF610_PAD_PTE23 = 128,
VF610_PAD_PTE24 = 129,
VF610_PAD_PTE25 = 130,
VF610_PAD_PTE26 = 131,
VF610_PAD_PTE27 = 132,
VF610_PAD_PTE28 = 133,
VF610_PAD_PTA7 = 134,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
IMX_PINCTRL_PIN(VF610_PAD_PTA6),
IMX_PINCTRL_PIN(VF610_PAD_PTA8),
IMX_PINCTRL_PIN(VF610_PAD_PTA9),
IMX_PINCTRL_PIN(VF610_PAD_PTA10),
IMX_PINCTRL_PIN(VF610_PAD_PTA11),
IMX_PINCTRL_PIN(VF610_PAD_PTA12),
IMX_PINCTRL_PIN(VF610_PAD_PTA16),
IMX_PINCTRL_PIN(VF610_PAD_PTA17),
IMX_PINCTRL_PIN(VF610_PAD_PTA18),
IMX_PINCTRL_PIN(VF610_PAD_PTA19),
IMX_PINCTRL_PIN(VF610_PAD_PTA20),
IMX_PINCTRL_PIN(VF610_PAD_PTA21),
IMX_PINCTRL_PIN(VF610_PAD_PTA22),
IMX_PINCTRL_PIN(VF610_PAD_PTA23),
IMX_PINCTRL_PIN(VF610_PAD_PTA24),
IMX_PINCTRL_PIN(VF610_PAD_PTA25),
MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
MX27_PAD_CLKO = PAD_ID(PF, 15),
MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
MX27_PAD_PC_READY = PAD_ID(PF, 17),
MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
MX27_PAD_CS4_B = PAD_ID(PF, 21),
MX27_PAD_CS5_B = PAD_ID(PF, 22),
MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
IMX_PINCTRL_PIN(MX27_PAD_LD0),
IMX_PINCTRL_PIN(MX27_PAD_LD1),
IMX_PINCTRL_PIN(MX27_PAD_LD2),
IMX_PINCTRL_PIN(MX27_PAD_LD3),
IMX_PINCTRL_PIN(MX27_PAD_LD4),
IMX_PINCTRL_PIN(MX27_PAD_LD5),
IMX_PINCTRL_PIN(MX27_PAD_LD6),
IMX_PINCTRL_PIN(MX27_PAD_LD7),
IMX_PINCTRL_PIN(MX27_PAD_LD8),
IMX_PINCTRL_PIN(MX27_PAD_LD9),
MX25_PAD_GPIO_D = 128,
MX25_PAD_GPIO_E = 129,
MX25_PAD_GPIO_F = 130,
MX25_PAD_EXT_ARMCLK = 131,
MX25_PAD_UPLL_BYPCLK = 132,
MX25_PAD_VSTBY_REQ = 133,
MX25_PAD_VSTBY_ACK = 134,
MX25_PAD_POWER_FAIL = 135,
MX25_PAD_CLKO = 136,
MX25_PAD_BOOT_MODE0 = 137,
MX25_PAD_BOOT_MODE1 = 138,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX25_PAD_A10),
IMX_PINCTRL_PIN(MX25_PAD_A13),
IMX_PINCTRL_PIN(MX25_PAD_A14),
IMX_PINCTRL_PIN(MX25_PAD_A15),
IMX_PINCTRL_PIN(MX25_PAD_A16),
IMX_PINCTRL_PIN(MX25_PAD_A17),
IMX_PINCTRL_PIN(MX25_PAD_A18),
IMX_PINCTRL_PIN(MX25_PAD_A19),
IMX_PINCTRL_PIN(MX25_PAD_A20),
IMX_PINCTRL_PIN(MX25_PAD_A21),
IMX_PINCTRL_PIN(MX25_PAD_A22),
IMX_PINCTRL_PIN(MX25_PAD_A23),
IMX_PINCTRL_PIN(MX25_PAD_A24),
IMX_PINCTRL_PIN(MX25_PAD_A25),
MX51_PAD_RESERVE113 = 356,
MX51_PAD_RESERVE114 = 357,
MX51_PAD_RESERVE115 = 358,
MX51_PAD_RESERVE116 = 359,
MX51_PAD_RESERVE117 = 360,
MX51_PAD_RESERVE118 = 361,
MX51_PAD_RESERVE119 = 362,
MX51_PAD_RESERVE120 = 363,
MX51_PAD_RESERVE121 = 364,
MX51_PAD_CSI1_PIXCLK = 365,
MX51_PAD_CSI1_MCLK = 366,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX51_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA0),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA1),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA2),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA3),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA4),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA5),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA6),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA7),
IMX_PINCTRL_PIN(MX51_PAD_EIM_DA8),
MX6DL_PAD_SD3_RST = 205,
MX6DL_PAD_SD4_CLK = 206,
MX6DL_PAD_SD4_CMD = 207,
MX6DL_PAD_SD4_DAT0 = 208,
MX6DL_PAD_SD4_DAT1 = 209,
MX6DL_PAD_SD4_DAT2 = 210,
MX6DL_PAD_SD4_DAT3 = 211,
MX6DL_PAD_SD4_DAT4 = 212,
MX6DL_PAD_SD4_DAT5 = 213,
MX6DL_PAD_SD4_DAT6 = 214,
MX6DL_PAD_SD4_DAT7 = 215,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6DL_PAD_RESERVE15),
MX6ULL_PAD_BOOT_MODE1 = 1,
MX6ULL_PAD_SNVS_TAMPER0 = 2,
MX6ULL_PAD_SNVS_TAMPER1 = 3,
MX6ULL_PAD_SNVS_TAMPER2 = 4,
MX6ULL_PAD_SNVS_TAMPER3 = 5,
MX6ULL_PAD_SNVS_TAMPER4 = 6,
MX6ULL_PAD_SNVS_TAMPER5 = 7,
MX6ULL_PAD_SNVS_TAMPER6 = 8,
MX6ULL_PAD_SNVS_TAMPER7 = 9,
MX6ULL_PAD_SNVS_TAMPER8 = 10,
MX6ULL_PAD_SNVS_TAMPER9 = 11,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
MX53_PAD_GPIO_9 = 199,
MX53_PAD_GPIO_3 = 200,
MX53_PAD_GPIO_6 = 201,
MX53_PAD_GPIO_2 = 202,
MX53_PAD_GPIO_4 = 203,
MX53_PAD_GPIO_5 = 204,
MX53_PAD_GPIO_7 = 205,
MX53_PAD_GPIO_8 = 206,
MX53_PAD_GPIO_16 = 207,
MX53_PAD_GPIO_17 = 208,
MX53_PAD_GPIO_18 = 209,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX53_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX53_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX53_PAD_GPIO_19),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW0),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW1),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_ROW2),
IMX_PINCTRL_PIN(MX53_PAD_KEY_COL3),
MX6SL_PAD_SD2_DAT7 = 158,
MX6SL_PAD_SD2_RST = 159,
MX6SL_PAD_SD3_CLK = 160,
MX6SL_PAD_SD3_CMD = 161,
MX6SL_PAD_SD3_DAT0 = 162,
MX6SL_PAD_SD3_DAT1 = 163,
MX6SL_PAD_SD3_DAT2 = 164,
MX6SL_PAD_SD3_DAT3 = 165,
MX6SL_PAD_UART1_RXD = 166,
MX6SL_PAD_UART1_TXD = 167,
MX6SL_PAD_WDOG_B = 168,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14),
IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15),
MX21_PAD_NFIO1 = PAD_ID(PF, 8),
MX21_PAD_NFIO2 = PAD_ID(PF, 9),
MX21_PAD_NFIO3 = PAD_ID(PF, 10),
MX21_PAD_NFIO4 = PAD_ID(PF, 11),
MX21_PAD_NFIO5 = PAD_ID(PF, 12),
MX21_PAD_NFIO6 = PAD_ID(PF, 13),
MX21_PAD_NFIO7 = PAD_ID(PF, 14),
MX21_PAD_CLKO = PAD_ID(PF, 15),
MX21_PAD_RESERVED = PAD_ID(PF, 16),
MX21_PAD_CS4 = PAD_ID(PF, 21),
MX21_PAD_CS5 = PAD_ID(PF, 22),
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
IMX_PINCTRL_PIN(MX21_PAD_LD0),
IMX_PINCTRL_PIN(MX21_PAD_LD1),
IMX_PINCTRL_PIN(MX21_PAD_LD2),
IMX_PINCTRL_PIN(MX21_PAD_LD3),
IMX_PINCTRL_PIN(MX21_PAD_LD4),
IMX_PINCTRL_PIN(MX21_PAD_LD5),
IMX_PINCTRL_PIN(MX21_PAD_LD6),
IMX_PINCTRL_PIN(MX21_PAD_LD7),
IMX_PINCTRL_PIN(MX21_PAD_LD8),
IMX_PINCTRL_PIN(MX21_PAD_LD9),
IMX_PINCTRL_PIN(MX21_PAD_LD10),
IMX_PINCTRL_PIN(MX21_PAD_LD11),
IMX_PINCTRL_PIN(MX21_PAD_LD12),
IMX_PINCTRL_PIN(MX21_PAD_LD13),
IMX_PINCTRL_PIN(MX21_PAD_LD14),
MX6SX_PAD_SD4_DATA0 = 160,
MX6SX_PAD_SD4_DATA1 = 161,
MX6SX_PAD_SD4_DATA2 = 162,
MX6SX_PAD_SD4_DATA3 = 163,
MX6SX_PAD_SD4_DATA4 = 164,
MX6SX_PAD_SD4_DATA5 = 165,
MX6SX_PAD_SD4_DATA6 = 166,
MX6SX_PAD_SD4_DATA7 = 167,
MX6SX_PAD_SD4_RESET_B = 168,
MX6SX_PAD_USB_H_DATA = 169,
MX6SX_PAD_USB_H_STROBE = 170,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
MX7D_PAD_ENET1_RGMII_RXC = 144,
MX7D_PAD_ENET1_RGMII_TD0 = 145,
MX7D_PAD_ENET1_RGMII_TD1 = 146,
MX7D_PAD_ENET1_RGMII_TD2 = 147,
MX7D_PAD_ENET1_RGMII_TD3 = 148,
MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
MX7D_PAD_ENET1_RGMII_TXC = 150,
MX7D_PAD_ENET1_TX_CLK = 151,
MX7D_PAD_ENET1_RX_CLK = 152,
MX7D_PAD_ENET1_CRS = 153,
MX7D_PAD_ENET1_COL = 154,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
MX8MQ_IOMUXC_I2C3_SDA = 138,
MX8MQ_IOMUXC_I2C4_SCL = 139,
MX8MQ_IOMUXC_I2C4_SDA = 140,
MX8MQ_IOMUXC_UART1_RXD = 141,
MX8MQ_IOMUXC_UART1_TXD = 142,
MX8MQ_IOMUXC_UART2_RXD = 143,
MX8MQ_IOMUXC_UART2_TXD = 144,
MX8MQ_IOMUXC_UART3_RXD = 145,
MX8MQ_IOMUXC_UART3_TXD = 146,
MX8MQ_IOMUXC_UART4_RXD = 147,
MX8MQ_IOMUXC_UART4_TXD = 148,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3),
IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04),
IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05),
