void send(LenBuffer data) { int nextByte = 0; // printf("send :: start of send\n"); while(!(IORD_ALTERA_AVALON_UART_STATUS(UART_BLUETOOTH_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BLUETOOTH_BASE, START_BYTE); // printf("send :: sending %i\n", START_BYTE); while(nextByte < data.len) { char byte = data.buf[nextByte++]; // printf("send :: Sending byte %i: '%i'\n", nextByte, byte); if(byte == START_BYTE || byte == END_BYTE || byte == ESCAPE_BYTE) { // printf("send :: Escaping byte %i: %i\n", nextByte, byte); while(!(IORD_ALTERA_AVALON_UART_STATUS(UART_BLUETOOTH_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BLUETOOTH_BASE, ESCAPE_BYTE); // printf("send :: sending %i\n", ESCAPE_BYTE); } while(!(IORD_ALTERA_AVALON_UART_STATUS(UART_BLUETOOTH_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BLUETOOTH_BASE, byte); // printf("send :: sending %i\n", byte); } //printf("send :: Out of Loop\n"); while(!(IORD_ALTERA_AVALON_UART_STATUS(UART_BLUETOOTH_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_BLUETOOTH_BASE, END_BYTE); // printf("send :: sending %i\n", END_BYTE); // printf("send :: end of send\n"); }
// Robot Commands: // 'P': Ping (Beep) // 'H': High Speed // 'L': Low Speed // 'S': Stop Robot // 'F': Forward // 'B': Backward // 'C': Clockwise // 'U': Counter-Clockwise void sendChar(char byte){ // Wait for transmit buffer to clear while(!(IORD_ALTERA_AVALON_UART_STATUS(XBEE_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); // Send the byte IOWR_ALTERA_AVALON_UART_TXDATA(XBEE_BASE, byte); // Wait for transmit buffer to clear while(!(IORD_ALTERA_AVALON_UART_STATUS(XBEE_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); }
/**************************************************************************** Function: void uart_send_byte(long Address, unsigned char data) Description: This function sends one Byte via the corresponding UART from the Address Precondition: Call uart_init(long Address, unsigned char flag) prior to use this function Parameters: long Address - UART Address unsigned char data - Data-Byte Returns: None Remarks: None ***************************************************************************/ void uart_send_byte(long Address, unsigned char data) { unsigned int status; IOWR_ALTERA_AVALON_UART_TXDATA(Address,data); status=IORD_ALTERA_AVALON_UART_STATUS(Address); while(!(status&0x0040)) { status=IORD_ALTERA_AVALON_UART_STATUS(Address); } }
void Uart_send(unsigned char data) { alt_u16 status; status = IORD_ALTERA_AVALON_UART_STATUS(RS232_BASE); while(!(status&0x0040))//waiting the tx_done { status = IORD_ALTERA_AVALON_UART_STATUS(RS232_BASE); } IOWR_ALTERA_AVALON_UART_TXDATA(RS232_BASE,data); }
/**************************************************************************** Function: unsigned char uart_receive_byte(long Address) Description: This function receives one Byte via the corresponding UART from the Address Precondition: Call uart_init(long Address, unsigned char flag) prior to use this function Parameters: long Address - UART Address Returns: unsigned char res - received Byte Remarks: None ***************************************************************************/ unsigned char uart_receive_byte(long Address) { unsigned int status; unsigned char res; status=IORD_ALTERA_AVALON_UART_STATUS(Address); while(!(status&0x0080)) { status=IORD_ALTERA_AVALON_UART_STATUS(Address); } res=IORD_ALTERA_AVALON_UART_RXDATA(Address); return res; }
int altera_avalon_uart_read(altera_avalon_uart_state* sp, char* ptr, int len, int flags) { int block; unsigned int status; block = !(flags & O_NONBLOCK); do { status = IORD_ALTERA_AVALON_UART_STATUS(sp->base); /* clear any error flags */ IOWR_ALTERA_AVALON_UART_STATUS(sp->base, 0); if (status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK) { ptr[0] = IORD_ALTERA_AVALON_UART_RXDATA(sp->base); if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK | ALTERA_AVALON_UART_STATUS_FE_MSK))) { return 1; } } } while (block); ALT_ERRNO = EWOULDBLOCK; return 0; }
static unsigned char altera_avalon_uart_getc(serial_channel *chan) { altera_avalon_uart_dev *uart_chan = (altera_avalon_uart_dev *)chan->dev_priv; cyg_addrword_t port = uart_chan->base; cyg_uint32 status; unsigned char data; do { do { status = IORD_ALTERA_AVALON_UART_STATUS(port); /* clear any error flags */ IOWR_ALTERA_AVALON_UART_STATUS(port, 0); } while (!(status & ALTERA_AVALON_UART_CONTROL_RRDY_MSK)); data = (unsigned char) IORD_ALTERA_AVALON_UART_RXDATA(port); } while (status & (ALTERA_AVALON_UART_STATUS_PE_MSK | ALTERA_AVALON_UART_STATUS_FE_MSK)); return data; }
void bluetoothIRQ(void* context) { char read = 0; while(!(IORD_ALTERA_AVALON_UART_STATUS(UART_BLUETOOTH_BASE) & ALTERA_AVALON_UART_STATUS_RRDY_MSK)); read = IORD_ALTERA_AVALON_UART_RXDATA(UART_BLUETOOTH_BASE); if(read == -1) { } else { // Debug stuff for LEDs if(read != START_BYTE && read != END_BYTE) { if(read == 'f') { charInter = 0x1; } else if(read == 'b') { charInter = 0x1; } else if(read == 'l') { charInter = 0x1; } else if(read == 'r') { charInter = 0x1; } else if(read == 's') { charInter = 0x0; } else { charInter = 0; } IOWR_8DIRECT(PIO_LEDS_BASE, 0, charInter | charRecv | curCommand | (sendCount << 4)); } OSQPost(byteQueue, (void*) read); } }
static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { const char * write_point = buffer; while(size--) { if(*write_point == '\n') { IOWR_ALTERA_AVALON_UART_TXDATA(RS232_BASE,'\r'); while( !(IORD_ALTERA_AVALON_UART_STATUS(RS232_BASE)&(1<<6)) ); // status bit6 : TRDY } IOWR_ALTERA_AVALON_UART_TXDATA(RS232_BASE,*write_point); write_point++; while( !(IORD_ALTERA_AVALON_UART_STATUS(RS232_BASE)&(1<<6)) ); // status bit6 : TRDY } return size; }
/** * Definition of the UART isr */ void ISRUART(void* context, unsigned int id) { unsigned int stat; INT8U chr; //get serial status stat = IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE); //character receiving if (stat & ALTERA_AVALON_UART_STATUS_RRDY_MSK) { //Check if UART is ready to offer access to the RXDATA register chr = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE); IOWR_ALTERA_AVALON_UART_STATUS(UART_0_BASE, 0); //clear the status bits again OSQPost(uartQsem, (void*) chr); //write new char in que } IOWR_ALTERA_AVALON_UART_STATUS(UART_0_BASE, 0); //reset interrupt }
static void serial_irq_0(void* context, alt_u32 id) { unsigned int stat; INT8U chr; //get serial status stat = IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE); //character Rx if (stat & ALTERA_AVALON_UART_STATUS_RRDY_MSK) { chr = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE); IOWR_ALTERA_AVALON_UART_STATUS(UART_0_BASE, 0); if (chr != 254) { OSQPost(qsemMsg, (void*) chr); } } IOWR_ALTERA_AVALON_UART_STATUS(UART_0_BASE, 0); }
static bool altera_avalon_uart_putc(serial_channel *chan, unsigned char c) { altera_avalon_uart_dev *uart_chan = (altera_avalon_uart_dev *)chan->dev_priv; cyg_addrword_t port = uart_chan->base; cyg_uint32 status; status = IORD_ALTERA_AVALON_UART_STATUS(port); if (!(uart_chan->flags & ALT_AVALON_UART_FC) || !(chan->config.flags & CYGNUM_SERIAL_FLOW_RTSCTS_TX) || (status & ALTERA_AVALON_UART_STATUS_CTS_MSK)) { if (status & ALTERA_AVALON_UART_STATUS_TRDY_MSK) { IOWR_ALTERA_AVALON_UART_TXDATA(port, c); return true; } } return false; }
static void vUARTInterruptHandler( void* context, alt_u32 id ) { alt_u32 status; /* Read the status register in order to determine the cause of the interrupt. */ status = IORD_ALTERA_AVALON_UART_STATUS( UART_BASE ); /* Clear any error flags set at the device */ IOWR_ALTERA_AVALON_UART_STATUS( UART_BASE, 0 ); /* process a read irq */ if ( status & ALTERA_AVALON_UART_STATUS_RRDY_MSK ) { vUARTReceiveHandler( status ); } /* process a write irq */ if ( status & ( ALTERA_AVALON_UART_STATUS_TRDY_MSK ) ) { vUARTTransmitHandler( status ); } }
// Entry point int main() { struct uart_pkt { unsigned char magic; #define UART_PKT_MAGIC 'N' // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | // | dir | dev | cnt | unsigned char mode; #define UART_PKT_MODE_CNT_MASK 0xF #define UART_PKT_MODE_CNT_SHIFT 0 #define UART_PKT_MODE_DEV_MASK 0x30 #define UART_PKT_MODE_DEV_SHIFT 4 #define UART_PKT_DEV_GPIO (0<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_LMS (1<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_VCTCXO (2<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_SI5338 (3<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_MODE_DIR_MASK 0xC0 #define UART_PKT_MODE_DIR_SHIFT 6 #define UART_PKT_MODE_DIR_READ (2<<UART_PKT_MODE_DIR_SHIFT) #define UART_PKT_MODE_DIR_WRITE (1<<UART_PKT_MODE_DIR_SHIFT) }; struct uart_cmd { unsigned char addr; unsigned char data; }; // Set the prescaler for 400kHz with an 80MHz clock (prescaer = clock / (5*desired) - 1) IOWR_16DIRECT(I2C, OC_I2C_PRESCALER, 39 ) ; IOWR_8DIRECT(I2C, OC_I2C_CTRL, OC_I2C_ENABLE ) ; // Set the UART divisor to 14 to get 4000000bps UART (baud rate = clock/(divisor + 1)) IOWR_ALTERA_AVALON_UART_DIVISOR(UART_0_BASE, 19) ; // Set the IQ Correction parameters to 0 IOWR_ALTERA_AVALON_PIO_DATA(IQ_CORR_RX_PHASE_GAIN_BASE, DEFAULT_CORRECTION); IOWR_ALTERA_AVALON_PIO_DATA(IQ_CORR_TX_PHASE_GAIN_BASE, DEFAULT_CORRECTION); /* Event loop never exits. */ { char state; enum { LOOKING_FOR_MAGIC, READING_MODE, READING_CMDS, EXECUTE_CMDS }; unsigned short i, cnt; unsigned char mode; unsigned char buf[14]; struct uart_cmd *cmd_ptr; uint32_t tmpvar = 0; state = LOOKING_FOR_MAGIC; while(1) { // Check if anything is in the FSK UART if( IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE) & ALTERA_AVALON_UART_STATUS_RRDY_MSK ) { uint8_t val ; int isRead; int isWrite; val = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE) ; switch (state) { case LOOKING_FOR_MAGIC: if (val == UART_PKT_MAGIC) state = READING_MODE; break; case READING_MODE: mode = val; if ((mode & UART_PKT_MODE_CNT_MASK) > 7) { mode &= ~UART_PKT_MODE_CNT_MASK; mode |= 7; } i = 0; cnt = (mode & UART_PKT_MODE_CNT_MASK) * sizeof(struct uart_cmd); state = READING_CMDS; break; case READING_CMDS: // cnt here means the number of bytes to read buf[i++] = val; if (!--cnt) state = EXECUTE_CMDS; break; default: break; } void write_uart(unsigned char val) { while (!(IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_0_BASE, val); } isRead = (mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_READ; isWrite = (mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_WRITE; if (state == EXECUTE_CMDS) { write_uart(UART_PKT_MAGIC); write_uart(mode); // cnt here means the number of commands cnt = (mode & UART_PKT_MODE_CNT_MASK); cmd_ptr = (struct uart_cmd *)buf; if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_LMS) { for (i = 0; i < cnt; i++) { if (isRead) { lms_spi_read(cmd_ptr->addr, &cmd_ptr->data); } else if (isWrite) { lms_spi_write(cmd_ptr->addr, cmd_ptr->data); cmd_ptr->data = 0; } else { cmd_ptr->addr = 0; cmd_ptr->data = 0; } cmd_ptr++; } } if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_SI5338) { for (i = 0; i < cnt; i++) { if (isRead) { uint8_t tmpvar; si5338_read(cmd_ptr->addr, &tmpvar); cmd_ptr->data = tmpvar; } else if (isWrite) { si5338_write(cmd_ptr->addr, cmd_ptr->data); cmd_ptr->data = 0; } else { cmd_ptr->addr = 0; cmd_ptr->data = 0; } cmd_ptr++; } } const struct { enum { GDEV_UNKNOWN, GDEV_GPIO, GDEV_IQ_CORR_RX, GDEV_IQ_CORR_TX, GDEV_FPGA_VERSION, GDEV_TIME_TIMER, GDEV_VCTXCO, GDEV_XB_LO, GDEV_EXPANSION, GDEV_EXPANSION_DIR, } gdev; int start, len; } gdev_lut[] = { {GDEV_GPIO, 0, 4}, {GDEV_IQ_CORR_RX, 4, 4}, {GDEV_IQ_CORR_TX, 8, 4}, {GDEV_FPGA_VERSION, 12, 4}, {GDEV_TIME_TIMER, 16, 16}, {GDEV_VCTXCO, 34, 2}, {GDEV_XB_LO, 36, 4}, {GDEV_EXPANSION, 40, 4}, {GDEV_EXPANSION_DIR, 44, 4}, }; #define ARRAY_SZ(x) (sizeof(x)/sizeof(x[0])) #define COLLECT_BYTES(x) tmpvar &= ~ ( 0xff << ( 8 * cmd_ptr->addr)); \ tmpvar |= cmd_ptr->data << (8 * cmd_ptr->addr); \ if (lastByte) { x; tmpvar = 0; } \ cmd_ptr->data = 0; if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_GPIO) { uint32_t device; int lut, lastByte; for (i = 0; i < cnt; i++) { device = GDEV_UNKNOWN; lastByte = 0; for (lut = 0; lut < ARRAY_SZ(gdev_lut); lut++) { if (gdev_lut[lut].start <= cmd_ptr->addr && (gdev_lut[lut].start + gdev_lut[lut].len) > cmd_ptr->addr) { cmd_ptr->addr -= gdev_lut[lut].start; device = gdev_lut[lut].gdev; lastByte = cmd_ptr->addr == (gdev_lut[lut].len - 1); break; } } if (isRead) { if (device == GDEV_FPGA_VERSION) cmd_ptr->data = (FPGA_VERSION >> (cmd_ptr->addr * 8)); else if (device == GDEV_TIME_TIMER) cmd_ptr->data = IORD_8DIRECT(TIME_TAMER, cmd_ptr->addr); else if (device == GDEV_GPIO) cmd_ptr->data = (IORD_ALTERA_AVALON_PIO_DATA(PIO_0_BASE)) >> (cmd_ptr->addr * 8); else if (device == GDEV_EXPANSION) cmd_ptr->data = (IORD_ALTERA_AVALON_PIO_DATA(PIO_1_BASE)) >> (cmd_ptr->addr * 8); else if (device == GDEV_EXPANSION_DIR) cmd_ptr->data = (IORD_ALTERA_AVALON_PIO_DATA(PIO_2_BASE)) >> (cmd_ptr->addr * 8); else if (device == GDEV_IQ_CORR_RX) cmd_ptr->data = (IORD_ALTERA_AVALON_PIO_DATA(IQ_CORR_RX_PHASE_GAIN_BASE)) >> (cmd_ptr->addr * 8); else if (device == GDEV_IQ_CORR_TX)
static void altera_avalon_uart_DSR(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t handle) { cyg_uint32 status, save_status = 0; serial_channel *chan = (serial_channel *)handle; altera_avalon_uart_dev *uart_chan = (altera_avalon_uart_dev *)chan->dev_priv; cyg_addrword_t port = uart_chan->base; cyg_uint32 data; bool canXmit = false; int space_avail; unsigned char* space; for (;;) { int num; bool canReceive = (chan->callbacks->data_rcv_req)(chan, 4096, &space_avail, &space) == CYG_RCV_OK; num = space_avail; if (!canReceive) { /* drop all receive chars we can't keep up */ for (;;) { status = IORD_ALTERA_AVALON_UART_STATUS(port); save_status |= status; IOWR_ALTERA_AVALON_UART_STATUS(port, 0); if (!(status & ALTERA_AVALON_UART_STATUS_RRDY_MSK)) { goto xmit; } data = IORD_ALTERA_AVALON_UART_RXDATA(port); } } while (space_avail > 0) { /* * Read the status register in order to determine the cause of the * interrupt. */ status = IORD_ALTERA_AVALON_UART_STATUS(port); save_status |= status; /* Clear any error flags set at the device */ IOWR_ALTERA_AVALON_UART_STATUS(port, 0); /* process a read irq */ if (status & ALTERA_AVALON_UART_STATUS_RRDY_MSK) { data = IORD_ALTERA_AVALON_UART_RXDATA(port); /* pass the data to the higher layers only if there was no error */ if (!(status & (ALTERA_AVALON_UART_STATUS_PE_MSK | ALTERA_AVALON_UART_STATUS_FE_MSK))) { //(chan->callbacks->rcv_char)(chan, data); *space++=data; space_avail--; } } else { (chan->callbacks->data_rcv_done)(chan, num-space_avail); goto xmit; } } (chan->callbacks->data_rcv_done)(chan, num-space_avail); } xmit: /* process a write irq */ if (save_status & (ALTERA_AVALON_UART_STATUS_TRDY_MSK | ALTERA_AVALON_UART_STATUS_DCTS_MSK)) { (chan->callbacks->xmt_char)(chan); } cyg_drv_interrupt_unmask(vector); }
void wifi_read() { int status = IORD_ALTERA_AVALON_UART_STATUS(UART_WIFI_BASE); printf("Wifi status: %d\n", status); char c = IORD_ALTERA_AVALON_UART_RXDATA(UART_WIFI_BASE); printf("Wifi: %c\n", c); }
// Entry point int main() { struct uart_pkt { unsigned char magic; #define UART_PKT_MAGIC 'N' // | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | // | dir | dev | cnt | unsigned char mode; #define UART_PKT_MODE_CNT_MASK 0xF #define UART_PKT_MODE_CNT_SHIFT 0 #define UART_PKT_MODE_DEV_MASK 0x30 #define UART_PKT_MODE_DEV_SHIFT 4 #define UART_PKT_DEV_GPIO (0<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_LMS (1<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_VCTCXO (2<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_DEV_SI5338 (3<<UART_PKT_MODE_DEV_SHIFT) #define UART_PKT_MODE_DIR_MASK 0xC0 #define UART_PKT_MODE_DIR_SHIFT 6 #define UART_PKT_MODE_DIR_READ (2<<UART_PKT_MODE_DIR_SHIFT) #define UART_PKT_MODE_DIR_WRITE (1<<UART_PKT_MODE_DIR_SHIFT) }; struct uart_cmd { unsigned char addr; unsigned char data; }; // Set the prescaler for 400kHz with an 80MHz clock (prescaer = clock / (5*desired) - 1) IOWR_16DIRECT(I2C, OC_I2C_PRESCALER, 39 ) ; IOWR_8DIRECT(I2C, OC_I2C_CTRL, OC_I2C_ENABLE ) ; // Set the UART divisor to 14 to get 4000000bps UART (baud rate = clock/(divisor + 1)) IOWR_ALTERA_AVALON_UART_DIVISOR(UART_0_BASE, 19) ; // Set the IQ Correction parameters to 0 IOWR_ALTERA_AVALON_PIO_DATA(IQ_CORR_RX_PHASE_GAIN_BASE, DEFAULT_CORRECTION); IOWR_ALTERA_AVALON_PIO_DATA(IQ_CORR_TX_PHASE_GAIN_BASE, DEFAULT_CORRECTION); /* Event loop never exits. */ { char state; enum { LOOKING_FOR_MAGIC, READING_MODE, READING_CMDS, EXECUTE_CMDS }; unsigned short i, cnt; unsigned char mode; unsigned char buf[14]; struct uart_cmd *cmd_ptr; uint16_t dacval; state = LOOKING_FOR_MAGIC; while(1) { // Check if anything is in the FSK UART if( IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE) & ALTERA_AVALON_UART_STATUS_RRDY_MSK ) { uint8_t val ; val = IORD_ALTERA_AVALON_UART_RXDATA(UART_0_BASE) ; switch (state) { case LOOKING_FOR_MAGIC: if (val == UART_PKT_MAGIC) state = READING_MODE; break; case READING_MODE: mode = val; if ((mode & UART_PKT_MODE_CNT_MASK) > 7) { mode &= ~UART_PKT_MODE_CNT_MASK; mode |= 7; } i = 0; cnt = (mode & UART_PKT_MODE_CNT_MASK) * sizeof(struct uart_cmd); state = READING_CMDS; break; case READING_CMDS: // cnt here means the number of bytes to read buf[i++] = val; if (!--cnt) state = EXECUTE_CMDS; break; default: break; } void write_uart(unsigned char val) { while (!(IORD_ALTERA_AVALON_UART_STATUS(UART_0_BASE) & ALTERA_AVALON_UART_STATUS_TRDY_MSK)); IOWR_ALTERA_AVALON_UART_TXDATA(UART_0_BASE, val); } if (state == EXECUTE_CMDS) { write_uart(UART_PKT_MAGIC); write_uart(mode); // cnt here means the number of commands cnt = (mode & UART_PKT_MODE_CNT_MASK); cmd_ptr = (struct uart_cmd *)buf; if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_LMS) { for (i = 0; i < cnt; i++) { if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_READ) { lms_spi_read(cmd_ptr->addr, &cmd_ptr->data); } else if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_WRITE) { lms_spi_write(cmd_ptr->addr, cmd_ptr->data); cmd_ptr->data = 0; } else { cmd_ptr->addr = 0; cmd_ptr->data = 0; } cmd_ptr++; } } if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_SI5338) { for (i = 0; i < cnt; i++) { if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_READ) { uint8_t tmpvar; si5338_read(cmd_ptr->addr, &tmpvar); cmd_ptr->data = tmpvar; } else if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_WRITE) { si5338_write(cmd_ptr->addr, cmd_ptr->data); cmd_ptr->data = 0; } else { cmd_ptr->addr = 0; cmd_ptr->data = 0; } cmd_ptr++; } } if ((mode & UART_PKT_MODE_DEV_MASK) == UART_PKT_DEV_GPIO) { uint32_t device; switch(cmd_ptr->addr) { case 0:case 1:case 2: case 3: device = PIO_0_BASE;break; case 4: case 5: case 6: case 7: device = IQ_CORR_RX_PHASE_GAIN_BASE; cmd_ptr->addr -= 4; break; case 8: case 9: case 10: case 11: device = IQ_CORR_TX_PHASE_GAIN_BASE; cmd_ptr->addr -= 8; break; case 12: case 13: case 14: case 15: device = FPGA_VERSION_ID; cmd_ptr->addr -= 12; break; default: //error device = PIO_0_BASE; } if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_READ) { if (device == FPGA_VERSION_ID) { cmd_ptr->data = (FPGA_VERSION >> (cmd_ptr->addr * 8)); } else { cmd_ptr->data = (IORD_ALTERA_AVALON_PIO_DATA(device)) >> (cmd_ptr->addr * 8); } } else if ((mode & UART_PKT_MODE_DIR_MASK) == UART_PKT_MODE_DIR_WRITE) {