int alt_timestamp_start(void)
{
void* base = altera_avalon_timer_ts_base;
if (!altera_avalon_timer_ts_freq)
{
return -1;
}
else
{
if(ALT_TIMESTAMP_COUNTER_SIZE == 64) {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIOD_0 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_1 (base, 0xFFFF);;
IOWR_ALTERA_AVALON_TIMER_PERIOD_2 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIOD_3 (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
} else {
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,ALTERA_AVALON_TIMER_CONTROL_STOP_MSK);
IOWR_ALTERA_AVALON_TIMER_PERIODL (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_PERIODH (base, 0xFFFF);
IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_START_MSK);
}
}
return 0;
}
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
void prvSetupTimerInterrupt( void )
{
/* Try to register the interrupt handler. */
if ( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
{
/* Failed to install the Interrupt Handler. */
asm( "break" );
}
else
{
/* Configure SysTick to interrupt at the requested rate. */
IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );
}
/* Clear any already pending interrupts generated by the Timer. */
IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
}
void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id,
alt_u32 irq, alt_u32 freq)
{
/* set the system clock frequency */
alt_sysclk_init (freq);
/* set to free running mode */
IOWR_ALTERA_AVALON_TIMER_CONTROL (base,
ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK);
/* register the interrupt handler, and enable the interrupt */
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq,
base, NULL);
#else
alt_irq_register (irq, base, alt_avalon_timer_sc_irq);
#endif
}
int main() {
alt_irq_register(TIMER_IRQ, (void*) 0, (void*) render);
IOWR_ALTERA_AVALON_TIMER_CONTROL (TIMER_BASE,
ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK);
/*
switch (get_mode()) {
case PS2_KEYBOARD: p_pos.y = 400; break;
case PS2_MOUSE: p_pos.y = 0; break;
default: p_pos.y = 100; break;
}
*/
init_vram();
render();
for (;;) {
get_key();
}
}
/*
* Initialize the timer IRQ given a base address, and register the function
* listed as the handler when IRQ is HI.
*
* Due to limitations of 32 bit, the longest period possible with this device
* is 858.9934592
*/
void init_timer_irq(alt_u32 base, alt_u32 irq_id, void * function, void * context, double secs) {
alt_u32 numticks = MAX_TICKS;
IOWR_ALTERA_AVALON_TIMER_STATUS(base, 0x0);
if(secs < 0) {
secs = -secs;
}
if(secs * TIMER_0_FREQ < MAX_TICKS) {
numticks = secs * TIMER_0_FREQ;
}
IOWR_ALTERA_AVALON_TIMER_PERIODH(base, numticks >> 16);
IOWR_ALTERA_AVALON_TIMER_PERIODL(base, numticks & ALTERA_AVALON_TIMER_PERIODL_MSK);
// alt_irq_context timer_context = alt_irq_disable_all();
alt_irq_register(TIMER_0_IRQ, context, function);
// alt_irq_enable_all(timer_context);
/*
* set the timeout period in number of clock cycles
*/
//set the timer period
/* set the control register bits:
* control[0] ITO = 1 enables IRQ generation once TO goes HI
* control[1] CONT = 1 sets the counter to restart once it hits zero
* control[2] START = 1 starts the counter - only works when register enabled
* control[3] STOP = 1 stops the counter - only works when register enabled
*/
IOWR_ALTERA_AVALON_TIMER_CONTROL(base,
ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
ALTERA_AVALON_TIMER_CONTROL_START_MSK
);
}
