/**
* Get BAM IRQ source and clear global IRQ status
*/
u32 bam_check_irq_source(void *base, u32 ee, u32 mask,
enum sps_callback_case *cb_case)
{
u32 source = bam_read_reg(base, IRQ_SRCS_EE(ee));
u32 clr = source & (1UL << 31);
if (clr) {
u32 status = 0;
status = bam_read_reg(base, IRQ_STTS);
if (status & IRQ_STTS_BAM_ERROR_IRQ) {
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_ERROR_IRQ\n",
(u32) base, status);
bam_output_register_content(base);
*cb_case = SPS_CALLBACK_BAM_ERROR_IRQ;
} else if (status & IRQ_STTS_BAM_HRESP_ERR_IRQ) {
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_HRESP_ERR_IRQ\n",
(u32) base, status);
bam_output_register_content(base);
*cb_case = SPS_CALLBACK_BAM_HRESP_ERR_IRQ;
} else
SPS_INFO("sps:bam 0x%x(va);bam irq status="
"0x%x.", (u32) base, status);
bam_write_reg(base, IRQ_CLR, status);
}
source &= (mask|(1UL << 31));
return source;
}
/**
* Get BAM IRQ source and clear global IRQ status
*/
u32 bam_check_irq_source(void *base, u32 ee, u32 mask)
{
u32 source = bam_read_reg(base, IRQ_SRCS_EE(ee));
u32 clr = source & (1UL << 31);
if (clr) {
u32 status = 0;
status = bam_read_reg(base, IRQ_STTS);
bam_write_reg(base, IRQ_CLR, status);
if (printk_ratelimit()) {
if (status & IRQ_STTS_BAM_ERROR_IRQ)
SPS_ERR("sps:bam 0x%x(va);bam irq status="
"0x%x.\nsps: BAM_ERROR_IRQ\n",
(u32) base, status);
else
SPS_INFO("sps:bam 0x%x(va);bam irq status="
"0x%x.", (u32) base, status);
}
}
source &= mask;
return source;
}
