__attribute__ ((naked)) void TIMER_0_ISR_0(void)
{
ISR_ENTER();
DEBUG("\nenter ISR\n");
irq_handler(TIMER_0, TIMER_0_DEV_0, TIMER_0_DEV_1);
DEBUG("leave ISR\n\n");
ISR_EXIT();
}
__attribute__((naked)) void isr_exti4_15(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR4) {
EXTI->PR |= EXTI_PR_PR4; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_4].cb();
}
else if (EXTI->PR & EXTI_PR_PR5) {
EXTI->PR |= EXTI_PR_PR5; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_5].cb();
}
else if (EXTI->PR & EXTI_PR_PR6) {
EXTI->PR |= EXTI_PR_PR6; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_6].cb();
}
else if (EXTI->PR & EXTI_PR_PR7) {
EXTI->PR |= EXTI_PR_PR7; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_7].cb();
}
else if (EXTI->PR & EXTI_PR_PR8) {
EXTI->PR |= EXTI_PR_PR8; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_8].cb();
}
else if (EXTI->PR & EXTI_PR_PR9) {
EXTI->PR |= EXTI_PR_PR9; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_9].cb();
}
else if (EXTI->PR & EXTI_PR_PR10) {
EXTI->PR |= EXTI_PR_PR10; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_10].cb();
}
else if (EXTI->PR & EXTI_PR_PR11) {
EXTI->PR |= EXTI_PR_PR11; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_11].cb();
}
else if (EXTI->PR & EXTI_PR_PR12) {
EXTI->PR |= EXTI_PR_PR12; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_12].cb();
}
else if (EXTI->PR & EXTI_PR_PR13) {
EXTI->PR |= EXTI_PR_PR13; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_13].cb();
}
else if (EXTI->PR & EXTI_PR_PR14) {
EXTI->PR |= EXTI_PR_PR14; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_14].cb();
}
else if (EXTI->PR & EXTI_PR_PR15) {
EXTI->PR |= EXTI_PR_PR15; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_15].cb();
}
ISR_EXIT();
}
__attribute__((naked)) void RTT_ISR(void)
{
ISR_ENTER();
if (RTT_DEV->CRL & RTC_CRL_ALRF) {
RTT_DEV->CRL &= ~(RTC_CRL_ALRF);
alarm_cb(alarm_arg);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti2_3(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR2) {
EXTI->PR |= EXTI_PR_PR2; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_2].cb();
}
else if (EXTI->PR & EXTI_PR_PR3) {
EXTI->PR |= EXTI_PR_PR3; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_3].cb();
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti0_1(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR0) {
EXTI->PR |= EXTI_PR_PR0; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_0].cb();
}
else if (EXTI->PR & EXTI_PR_PR1) {
EXTI->PR |= EXTI_PR_PR1; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_1].cb();
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti4(void)
{
ISR_ENTER();
if (EXTI->PR & EXTI_PR_PR4) {
EXTI->PR |= EXTI_PR_PR4; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_4].cb(config[GPIO_IRQ_4].arg);
}
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
void TIMER_2_ISR2(void)
{
ISR_ENTER();
uint32_t status = TIMER_2_DEV->TC_CHANNEL[1].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPAS;
config[TIMER_2].cb(3);
}
else if (status & TC_SR_CPBS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPBS;
config[TIMER_2].cb(4);
}
else if (status & TC_SR_CPCS) {
TIMER_2_DEV->TC_CHANNEL[1].TC_IDR = TC_IDR_CPCS;
config[TIMER_2].cb(5);
}
ISR_EXIT();
}
void TIMER_1_ISR1(void)
{
ISR_ENTER();
uint32_t status = TIMER_1_DEV->TC_CHANNEL[0].TC_SR;
if (status & TC_SR_CPAS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPAS;
config[TIMER_1].cb(0);
}
if (status & TC_SR_CPBS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPBS;
config[TIMER_1].cb(1);
}
if (status & TC_SR_CPCS) {
TIMER_1_DEV->TC_CHANNEL[0].TC_IDR = TC_IDR_CPCS;
config[TIMER_1].cb(2);
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti15_10(void)
{
ISR_ENTER();
#ifdef GPIO_IRQ_10
if (EXTI->PR & EXTI_PR_PR10) {
EXTI->PR |= EXTI_PR_PR10; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_10].cb(config[GPIO_IRQ_10].arg);
}
#endif
#ifdef GPIO_IRQ_11
if (EXTI->PR & EXTI_PR_PR11) {
EXTI->PR |= EXTI_PR_PR11; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_11].cb(config[GPIO_IRQ_11].arg);
}
#endif
#ifdef GPIO_IRQ_12
if (EXTI->PR & EXTI_PR_PR12) {
EXTI->PR |= EXTI_PR_PR12; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_12].cb(config[GPIO_IRQ_12].arg);
}
#endif
#ifdef GPIO_IRQ_13
if (EXTI->PR & EXTI_PR_PR13) {
EXTI->PR |= EXTI_PR_PR13; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_13].cb(config[GPIO_IRQ_13].arg);
}
#endif
#ifdef GPIO_IRQ_14
if (EXTI->PR & EXTI_PR_PR14) {
EXTI->PR |= EXTI_PR_PR14; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_14].cb(config[GPIO_IRQ_14].arg);
}
#endif
#ifdef GPIO_IRQ_15
if (EXTI->PR & EXTI_PR_PR15) {
EXTI->PR |= EXTI_PR_PR15; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_15].cb(config[GPIO_IRQ_15].arg);
}
#endif
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__((naked)) void isr_exti9_5(void)
{
ISR_ENTER();
#ifdef GPIO_IRQ_5
if (EXTI->PR & EXTI_PR_PR5) {
EXTI->PR |= EXTI_PR_PR5; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_5].cb(config[GPIO_IRQ_5].arg);
}
#endif
#ifdef GPIO_IRQ_6
if (EXTI->PR & EXTI_PR_PR6) {
EXTI->PR |= EXTI_PR_PR6; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_6].cb(config[GPIO_IRQ_6].arg);
}
#endif
#ifdef GPIO_IRQ_7
if (EXTI->PR & EXTI_PR_PR7) {
EXTI->PR |= EXTI_PR_PR7; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_7].cb(config[GPIO_IRQ_7].arg);
}
#endif
#ifdef GPIO_IRQ_8
if (EXTI->PR & EXTI_PR_PR8) {
EXTI->PR |= EXTI_PR_PR8; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_8].cb(config[GPIO_IRQ_8].arg);
}
#endif
#ifdef GPIO_IRQ_9
if (EXTI->PR & EXTI_PR_PR9) {
EXTI->PR |= EXTI_PR_PR9; /* clear status bit by writing a 1 to it */
config[GPIO_IRQ_9].cb(config[GPIO_IRQ_9].arg);
}
#endif
if (sched_context_switch_request) {
thread_yield();
}
ISR_EXIT();
}
__attribute__ ((naked)) void TIMER_0_ISR(void)
{
ISR_ENTER();
irq_handler(TIMER_0, TIMER_0_DEV);
ISR_EXIT();
}
__attribute__((naked)) void UART_2_ISR(void)
{
ISR_ENTER();
irq_handler(UART_2, UART_2_DEV);
ISR_EXIT();
}
