/**
* @brief Deinitializes the CANx peripheral registers to their default reset values.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
{
/* Check CAN handle */
if(hcan == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY;
/* DeInit the low level hardware */
HAL_CAN_MspDeInit(hcan);
/* Change CAN state */
hcan->State = HAL_CAN_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hcan);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
uint32_t tickstart = 0;
/* Check CAN handle */
if(hcan == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
assert_param(IS_CAN_SJW(hcan->Init.SJW));
assert_param(IS_CAN_BS1(hcan->Init.BS1));
assert_param(IS_CAN_BS2(hcan->Init.BS2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
if(hcan->State == HAL_CAN_STATE_RESET)
{
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
/* Initialize the CAN state*/
hcan->State = HAL_CAN_STATE_BUSY;
/* Exit from sleep mode */
hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
/* Request initialisation */
hcan->Instance->MCR |= CAN_MCR_INRQ ;
/* Get tickstart */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
/* Check acknowledge */
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_TTCM;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
}
/* Set the automatic bus-off management */
if (hcan->Init.ABOM == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_ABOM;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
}
/* Set the automatic wake-up mode */
if (hcan->Init.AWUM == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_AWUM;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
}
/* Set the no automatic retransmission */
if (hcan->Init.NART == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_NART;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
}
/* Set the receive FIFO locked mode */
if (hcan->Init.RFLM == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_RFLM;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
}
/* Set the transmit FIFO priority */
if (hcan->Init.TXFP == ENABLE)
{
hcan->Instance->MCR |= CAN_MCR_TXFP;
}
else
{
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
}
/* Set the bit timing register */
hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
((uint32_t)hcan->Init.SJW) | \
((uint32_t)hcan->Init.BS1) | \
((uint32_t)hcan->Init.BS2) | \
((uint32_t)hcan->Init.Prescaler - 1);
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
if((HAL_GetTick() - tickstart) > HAL_CAN_DEFAULT_TIMEOUT)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
}
/* Check acknowledged */
if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
status = CAN_INITSTATUS_SUCCESS;
}
}
if(status == CAN_INITSTATUS_SUCCESS)
{
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
}
}
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
* @param hcan: pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */
uint32_t tickstart = 0;
uint32_t tmp_mcr = 0;
/* Check CAN handle */
if(hcan == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
assert_param(IS_CAN_SJW(hcan->Init.SJW));
assert_param(IS_CAN_BS1(hcan->Init.BS1));
assert_param(IS_CAN_BS2(hcan->Init.BS2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
if(hcan->State == HAL_CAN_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcan->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CAN_MspInit(hcan);
}
/* Initialize the CAN state*/
hcan->State = HAL_CAN_STATE_BUSY;
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
/* Check acknowledge */
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_TTCM);
}
/* Set the automatic bus-off management */
if (hcan->Init.ABOM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_ABOM);
}
/* Set the automatic wake-up mode */
if (hcan->Init.AWUM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_AWUM);
}
/* Set the no automatic retransmission */
if (hcan->Init.NART == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_NART);
}
/* Set the receive FIFO locked mode */
if (hcan->Init.RFLM == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_RFLM);
}
/* Set the transmit FIFO priority */
if (hcan->Init.TXFP == ENABLE)
{
SET_BIT(tmp_mcr, CAN_MCR_TXFP);
}
/* Update register MCR */
MODIFY_REG(hcan->Instance->MCR,
CAN_MCR_TTCM |
CAN_MCR_ABOM |
CAN_MCR_AWUM |
CAN_MCR_NART |
CAN_MCR_RFLM |
CAN_MCR_TXFP,
tmp_mcr);
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
hcan->Init.SJW |
hcan->Init.BS1 |
hcan->Init.BS2 |
(hcan->Init.Prescaler - 1) ));
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while(HAL_IS_BIT_CLR(hcan->Instance->MSR, CAN_MSR_INAK))
{
if((HAL_GetTick()-tickstart) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
/* Check acknowledged */
if (HAL_IS_BIT_SET(hcan->Instance->MSR, CAN_MSR_INAK))
{
status = CAN_INITSTATUS_SUCCESS;
}
}
if(status == CAN_INITSTATUS_SUCCESS)
{
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Return function status */
return HAL_OK;
}
else
{
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
}
}
