void init_VISWS_APIC_irqs(void)
{
	int i;

	for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = 0;
		irq_desc[i].depth = 1;

		if (i == 0) {
			irq_desc[i].chip = &cobalt_irq_type;
		}
		else if (i == CO_IRQ_IDE0) {
			irq_desc[i].chip = &cobalt_irq_type;
		}
		else if (i == CO_IRQ_IDE1) {
			irq_desc[i].chip = &cobalt_irq_type;
		}
		else if (i == CO_IRQ_8259) {
			irq_desc[i].chip = &piix4_master_irq_type;
		}
		else if (i < CO_IRQ_APIC0) {
			irq_desc[i].chip = &piix4_virtual_irq_type;
		}
		else if (IS_CO_APIC(i)) {
			irq_desc[i].chip = &cobalt_irq_type;
		}
	}

	setup_irq(CO_IRQ_8259, &master_action);
	setup_irq(2, &cascade_action);
}
示例#2
0
static void __init visws_pre_intr_init(void)
{
	int i;

	set_piix4_virtual_irq_type();

	for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
		struct irq_chip *chip = NULL;

		if (i == 0)
			chip = &cobalt_irq_type;
		else if (i == CO_IRQ_IDE0)
			chip = &cobalt_irq_type;
		else if (i == CO_IRQ_IDE1)
			>chip = &cobalt_irq_type;
		else if (i == CO_IRQ_8259)
			chip = &piix4_master_irq_type;
		else if (i < CO_IRQ_APIC0)
			chip = &piix4_virtual_irq_type;
		else if (IS_CO_APIC(i))
			chip = &cobalt_irq_type;

		if (chip)
			irq_set_chip(i, chip);
	}
static int is_co_apic(unsigned int irq)
{
	if (IS_CO_APIC(irq))
		return CO_APIC(irq);

	switch (irq) {
		case 0: return CO_APIC_CPU;
		case CO_IRQ_IDE0: return co_apic_ide0_hack();
		case CO_IRQ_IDE1: return CO_APIC_IDE1;
		default: return -1;
	}
}