/** * @brief Initializes the FSMC_PCCARD device according to the specified * control parameters in the FSMC_PCCARD_HandleTypeDef * @param Device Pointer to PCCARD device instance * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) { uint32_t tmpr = 0U; /* Check the parameters */ assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); /* Get PCCARD control register value */ tmpr = Device->PCR4; /* Clear TAR, TCLR, PWAITEN and PWID bits */ tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ FSMC_PCR4_PWID)); /* Set FSMC_PCCARD device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ (Init->TCLRSetupTime << 9U) |\ (Init->TARSetupTime << 13U)); Device->PCR4 = tmpr; return HAL_OK; }
/** * @brief Initializes the FSMC_NAND device according to the specified * control parameters in the FSMC_NAND_HandleTypeDef * @param Device Pointer to NAND device instance * @param Init Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) { uint32_t tmpr = 0U; /* Check the parameters */ assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); if(Init->NandBank == FSMC_NAND_BANK2) { /* Get the NAND bank 2 register value */ tmpr = Device->PCR2; } else { /* Get the NAND bank 3 register value */ tmpr = Device->PCR3; } /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); /* Set NAND device control parameters */ tmpr |= (uint32_t)(Init->Waitfeature |\ FSMC_PCR_MEMORY_TYPE_NAND |\ Init->MemoryDataWidth |\ Init->EccComputation |\ Init->ECCPageSize |\ ((Init->TCLRSetupTime) << 9U) |\ ((Init->TARSetupTime) << 13U)); if(Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ Device->PCR2 = tmpr; } else { /* NAND bank 3 registers configuration */ Device->PCR3 = tmpr; } return HAL_OK; }
/** * @brief Initializes the FSMC_PCCARD device according to the specified * control parameters in the FSMC_PCCARD_HandleTypeDef * @param Device: Pointer to PCCARD device instance * @param Init: Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); /* Set FSMC_PCCARD device control parameters */ Device->PCR4 = (uint32_t)(Init->Waitfeature |\ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ (Init->TCLRSetupTime << 9) |\ (Init->TARSetupTime << 13)); return HAL_OK; }
/** * @brief Initializes the FSMC_PCCARD device according to the specified * control parameters in the FSMC_PCCARD_HandleTypeDef * @param Device: Pointer to PCCARD device instance * @param Init: Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FSMC_PCCARD_DEVICE(Device)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); /* Set FSMC_PCCARD device control parameters */ MODIFY_REG(Device->PCR4, \ (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID | FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \ (FSMC_PCR_MEMORY_TYPE_PCCARD | \ Init->Waitfeature | \ FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | \ (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \ (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR)))); return HAL_OK; }
/** * @brief Initializes the FSMC_NAND device according to the specified * control parameters in the FSMC_NAND_HandleTypeDef * @param Device: Pointer to NAND device instance * @param Init: Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); if(Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |\ FSMC_PCR_MEMORY_TYPE_NAND |\ Init->MemoryDataWidth |\ Init->EccComputation |\ Init->ECCPageSize |\ ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) |\ ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); } else { /* NAND bank 3 registers configuration */ MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |\ FSMC_PCR_MEMORY_TYPE_NAND |\ Init->MemoryDataWidth |\ Init->EccComputation |\ Init->ECCPageSize |\ ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) |\ ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); } return HAL_OK; }
/** * @brief Initializes the FSMC_NAND device according to the specified * control parameters in the FSMC_NAND_HandleTypeDef * @param Device: Pointer to NAND device instance * @param Init: Pointer to NAND Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) { uint32_t tmppcr = 0; /* Check the parameters */ assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); /* Set NAND device control parameters */ tmppcr = (uint32_t)(Init->Waitfeature |\ FSMC_PCR_MEMORY_TYPE_NAND |\ Init->MemoryDataWidth |\ Init->EccComputation |\ Init->ECCPageSize |\ ((Init->TCLRSetupTime) << 9) |\ ((Init->TARSetupTime) << 13) ); if(Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ Device->PCR2 = tmppcr; } else { /* NAND bank 3 registers configuration */ Device->PCR3 = tmppcr; } return HAL_OK; }