void rtl8821au_firmware_selfreset(struct rtl_priv *rtlpriv) { struct rtl_hal *rtlhal = rtl_hal(rtlpriv); uint8_t u1bTmp, u1bTmp2; /* Reset MCU IO Wrapper- sugggest by SD1-Gimmy */ if (IS_HARDWARE_TYPE_8812(rtlhal)) { u1bTmp2 = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1bTmp2&(~BIT3)); } else if (IS_HARDWARE_TYPE_8821(rtlhal)) { u1bTmp2 = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1bTmp2&(~BIT0)); } u1bTmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1); rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); /* Enable MCU IO Wrapper */ if (IS_HARDWARE_TYPE_8812(rtlhal)) { u1bTmp2 = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1bTmp2 | (BIT3)); } else if (IS_HARDWARE_TYPE_8821(rtlhal)) { u1bTmp2 = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1); rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1bTmp2 | (BIT0)); } rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2)); RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " _8051Reset8812(): 8051 reset success .\n"); }
static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz ,u8 bagg_pkt) { int pull=0; uint qsel; u8 data_rate,pwr_status,offset; _adapter *padapter = pxmitframe->padapter; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct pkt_attrib *pattrib = &pxmitframe->attrib; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); struct dm_priv *pdmpriv = &pHalData->dmpriv; u8 *ptxdesc = pmem; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); sint bmcst = IS_MCAST(pattrib->ra); #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX if (padapter->registrypriv.mp_mode == 0) { if((PACKET_OFFSET_SZ != 0) && (!bagg_pkt) &&(rtw_usb_bulk_size_boundary(padapter,TXDESC_SIZE+sz)==_FALSE)) { ptxdesc = (pmem+PACKET_OFFSET_SZ); //DBG_8192C("==> non-agg-pkt,shift pointer...\n"); pull = 1; } } #endif // CONFIG_USE_USB_BUFFER_ALLOC_TX _rtw_memset(ptxdesc, 0, TXDESC_SIZE); //4 offset 0 SET_TX_DESC_FIRST_SEG_8812(ptxdesc, 1); SET_TX_DESC_LAST_SEG_8812(ptxdesc, 1); SET_TX_DESC_OWN_8812(ptxdesc, 1); //DBG_8192C("%s==> pkt_len=%d,bagg_pkt=%02x\n",__FUNCTION__,sz,bagg_pkt); SET_TX_DESC_PKT_SIZE_8812(ptxdesc, sz); offset = TXDESC_SIZE + OFFSET_SZ; #ifdef CONFIG_TX_EARLY_MODE if(bagg_pkt){ offset += EARLY_MODE_INFO_SIZE ;//0x28 } #endif //DBG_8192C("%s==>offset(0x%02x) \n",__FUNCTION__,offset); SET_TX_DESC_OFFSET_8812(ptxdesc, offset); if (bmcst) { SET_TX_DESC_BMC_8812(ptxdesc, 1); } #ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX if (padapter->registrypriv.mp_mode == 0) { if((PACKET_OFFSET_SZ != 0) && (!bagg_pkt)){ if((pull) && (pxmitframe->pkt_offset>0)) { pxmitframe->pkt_offset = pxmitframe->pkt_offset -1; } } } #endif //DBG_8192C("%s, pkt_offset=0x%02x\n",__FUNCTION__,pxmitframe->pkt_offset); // pkt_offset, unit:8 bytes padding if (pxmitframe->pkt_offset > 0) { SET_TX_DESC_PKT_OFFSET_8812(ptxdesc, pxmitframe->pkt_offset); } SET_TX_DESC_MACID_8812(ptxdesc, pattrib->mac_id); SET_TX_DESC_RATE_ID_8812(ptxdesc, pattrib->raid); SET_TX_DESC_QUEUE_SEL_8812(ptxdesc, pattrib->qsel); //offset 12 if (!pattrib->qos_en) { SET_TX_DESC_HWSEQ_EN_8812(ptxdesc, 1); // Hw set sequence number } else { SET_TX_DESC_SEQ_8812(ptxdesc, pattrib->seqnum); } if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) { //DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); rtl8812a_fill_txdesc_sectype(pattrib, ptxdesc); //offset 20 #ifdef CONFIG_USB_TX_AGGREGATION if (pxmitframe->agg_num > 1){ //DBG_8192C("%s agg_num:%d\n",__FUNCTION__,pxmitframe->agg_num ); SET_TX_DESC_USB_TXAGG_NUM_8812(ptxdesc, pxmitframe->agg_num); } #endif rtl8812a_fill_txdesc_vcs(padapter, pattrib, ptxdesc); if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && (pattrib->ether_type != 0x88b4) && (pattrib->dhcp_pkt != 1) #ifdef CONFIG_AUTO_AP_MODE && (pattrib->pctrl != _TRUE) #endif ) { //Non EAP & ARP & DHCP type data packet if (pattrib->ampdu_en==_TRUE) { SET_TX_DESC_AGG_ENABLE_8812(ptxdesc, 1); SET_TX_DESC_MAX_AGG_NUM_8812(ptxdesc, 0x1f); // Set A-MPDU aggregation. SET_TX_DESC_AMPDU_DENSITY_8812(ptxdesc, pattrib->ampdu_spacing); } else { SET_TX_DESC_AGG_BREAK_8812(ptxdesc, 1); } rtl8812a_fill_txdesc_phy(padapter, pattrib, ptxdesc); //DATA Rate FB LMT SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(ptxdesc, 0x1f); if (pHalData->fw_ractrl == _FALSE) { SET_TX_DESC_USE_RATE_8812(ptxdesc, 1); if(pdmpriv->INIDATA_RATE[pattrib->mac_id] & BIT(7)) SET_TX_DESC_DATA_SHORT_8812(ptxdesc, 1); SET_TX_DESC_TX_RATE_8812(ptxdesc, (pdmpriv->INIDATA_RATE[pattrib->mac_id] & 0x7F)); } if (padapter->fix_rate != 0xFF) { // modify data rate by iwpriv SET_TX_DESC_USE_RATE_8812(ptxdesc, 1); if(padapter->fix_rate & BIT(7)) SET_TX_DESC_DATA_SHORT_8812(ptxdesc, 1); SET_TX_DESC_TX_RATE_8812(ptxdesc, (padapter->fix_rate & 0x7F)); if (!padapter->data_fb) SET_TX_DESC_DISABLE_FB_8812(ptxdesc,1); } if (pattrib->ldpc) SET_TX_DESC_DATA_LDPC_8812(ptxdesc, 1); if (pattrib->stbc) SET_TX_DESC_DATA_STBC_8812(ptxdesc, 1); } else { // EAP data packet and ARP packet and DHCP. // Use the 1M data rate to send the EAP/ARP packet. // This will maybe make the handshake smooth. SET_TX_DESC_USE_RATE_8812(ptxdesc, 1); SET_TX_DESC_AGG_BREAK_8812(ptxdesc, 1); // HW will ignore this setting if the transmission rate is legacy OFDM. if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) { SET_TX_DESC_DATA_SHORT_8812(ptxdesc, 1); } SET_TX_DESC_TX_RATE_8812(ptxdesc, MRateToHwRate(pmlmeext->tx_rate)); } #ifdef CONFIG_TDLS #ifdef CONFIG_XMIT_ACK /* CCX-TXRPT ack for xmit mgmt frames. */ if (pxmitframe->ack_report) { SET_TX_DESC_SPE_RPT_8812(ptxdesc, 1); #ifdef DBG_CCX DBG_871X("%s set tx report\n", __func__); #endif } #endif /* CONFIG_XMIT_ACK */ #endif } else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) { //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); if(IS_HARDWARE_TYPE_8821(padapter)) SET_TX_DESC_MBSSID_8821(ptxdesc, pattrib->mbssid); SET_TX_DESC_USE_RATE_8812(ptxdesc, 1); #ifdef CONFIG_INTEL_PROXIM if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){ DBG_871X("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate); SET_TX_DESC_TX_RATE_8812(ptxdesc, pattrib->rate); } else #endif { SET_TX_DESC_TX_RATE_8812(ptxdesc, MRateToHwRate(pattrib->rate)); } // VHT NDPA or HT NDPA Packet for Beamformer. if((pattrib->subtype == WIFI_NDPA) || ((pattrib->subtype == WIFI_ACTION_NOACK) && (pattrib->order == 1))) { SET_TX_DESC_NAV_USE_HDR_8812(ptxdesc, 1); SET_TX_DESC_DATA_BW_8812(ptxdesc, BWMapping_8812(padapter,pattrib)); SET_TX_DESC_RTS_SC_8812(ptxdesc, SCMapping_8812(padapter,pattrib)); SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(ptxdesc, 1); SET_TX_DESC_DATA_RETRY_LIMIT_8812(ptxdesc, 5); SET_TX_DESC_DISABLE_FB_8812(ptxdesc, 1); //if(pattrib->rts_cca) //{ // SET_TX_DESC_NDPA_8812(ptxdesc, 2); //} //else { SET_TX_DESC_NDPA_8812(ptxdesc, 1); } } else { SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(ptxdesc, 1); if (pattrib->retry_ctrl == _TRUE) { SET_TX_DESC_DATA_RETRY_LIMIT_8812(ptxdesc, 6); } else { SET_TX_DESC_DATA_RETRY_LIMIT_8812(ptxdesc, 12); } } #ifdef CONFIG_XMIT_ACK //CCX-TXRPT ack for xmit mgmt frames. if (pxmitframe->ack_report) { SET_TX_DESC_SPE_RPT_8812(ptxdesc, 1); #ifdef DBG_CCX DBG_871X("%s set tx report\n", __func__); #endif } #endif //CONFIG_XMIT_ACK } else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) { DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); } #ifdef CONFIG_MP_INCLUDED else if(((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) && (padapter->registrypriv.mp_mode == 1)) { fill_txdesc_for_mp(padapter, ptxdesc); } #endif else { DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); SET_TX_DESC_USE_RATE_8812(ptxdesc, 1); SET_TX_DESC_TX_RATE_8812(ptxdesc, MRateToHwRate(pmlmeext->tx_rate)); } rtl8812a_cal_txdesc_chksum(ptxdesc); _dbg_dump_tx_info(padapter,pxmitframe->frame_tag,ptxdesc); return pull; }
static void dm_CheckPbcGPIO(_adapter *padapter) { u8 tmp1byte; u8 bPbcPressed = _FALSE; if(!padapter->registrypriv.hw_wps_pbc) return; #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) if (IS_HARDWARE_TYPE_8812(padapter)) { tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT); rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode tmp1byte =rtw_read8(padapter, GPIO_IN); if (tmp1byte == 0xff) return ; if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT) { bPbcPressed = _TRUE; } } else if (IS_HARDWARE_TYPE_8821(padapter)) { tmp1byte = rtw_read8(padapter, GPIO_IO_SEL_8811A); tmp1byte |= (BIT4); rtw_write8(padapter, GPIO_IO_SEL_8811A, tmp1byte); //enable GPIO[2] as output mode tmp1byte &= ~(BIT4); rtw_write8(padapter, GPIO_IN_8811A, tmp1byte); //reset the floating voltage level tmp1byte = rtw_read8(padapter, GPIO_IO_SEL_8811A); tmp1byte &= ~(BIT4); rtw_write8(padapter, GPIO_IO_SEL_8811A, tmp1byte); //enable GPIO[2] as input mode tmp1byte =rtw_read8(padapter, GPIO_IN_8811A); if (tmp1byte == 0xff) return ; if (tmp1byte&BIT4) { bPbcPressed = _TRUE; } } #else #endif if( _TRUE == bPbcPressed) { // Here we only set bPbcPressed to true // After trigger PBC, the variable will be set to false DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); rtw_request_wps_pbc_event(padapter); } }
//============================================================ // functions //============================================================ static void Init_ODM_ComInfo_8812(PADAPTER Adapter) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); struct dm_priv *pdmpriv = &pHalData->dmpriv; PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); u8 cut_ver,fab_ver; u8 BoardType = ODM_BOARD_DEFAULT; // // Init Value // memset(pDM_Odm,0,sizeof(*pDM_Odm)); pDM_Odm->Adapter = Adapter; ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE); if (Adapter->interface_type == RTW_GSPI) ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO); else ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type); if (IS_HARDWARE_TYPE_8812(Adapter)) ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8812); else if (IS_HARDWARE_TYPE_8821(Adapter)) ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8821); fab_ver = ODM_TSMC; if(IS_A_CUT(pHalData->VersionID)) cut_ver = ODM_CUT_A; else if(IS_B_CUT(pHalData->VersionID)) cut_ver = ODM_CUT_B; else if(IS_C_CUT(pHalData->VersionID)) cut_ver = ODM_CUT_C; else if(IS_D_CUT(pHalData->VersionID)) cut_ver = ODM_CUT_D; else if(IS_E_CUT(pHalData->VersionID)) cut_ver = ODM_CUT_E; else cut_ver = ODM_CUT_A; ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver); ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID)); //1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) if(pHalData->InterfaceSel == INTF_SEL1_USB_High_Power) { ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); } else { ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, pHalData->ExternalPA_2G); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 0); } #else // PCIE no external PA now??? ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 0); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 0); #endif if (pHalData->ExternalLNA_2G != 0) { BoardType |= ODM_BOARD_EXT_LNA; ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); } if (pHalData->ExternalLNA_5G != 0) { BoardType |= ODM_BOARD_EXT_LNA_5G; ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1); } if (pHalData->ExternalPA_2G != 0) { BoardType |= ODM_BOARD_EXT_PA; ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); } if (pHalData->ExternalPA_5G != 0) { BoardType |= ODM_BOARD_EXT_PA_5G; ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1); } ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, BoardType); //1 ============== End of BoardType ============== ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->RFEType); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pEEPROM->CustomerID); // ODM_CMNINFO_BINHCT_TEST only for MP Team ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec); if(pHalData->rf_type == RF_1T1R){ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R); } else if(pHalData->rf_type == RF_2T2R){ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R); } else if(pHalData->rf_type == RF_1T2R){ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R); } ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->RFEType); ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); #ifdef CONFIG_DISABLE_ODM pdmpriv->InitODMFlag = 0; #else pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | ODM_RF_TX_PWR_TRACK //| ; //if(pHalData->AntDivCfg) // pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; #endif ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); }
static void PHY_HandleSwChnlAndSetBW8812(struct rtl_priv *rtlpriv, BOOLEAN bSwitchChannel, BOOLEAN bSetBandWidth, uint8_t ChannelNum, enum CHANNEL_WIDTH ChnlWidth, uint8_t ChnlOffsetOf40MHz, uint8_t ChnlOffsetOf80MHz, uint8_t CenterFrequencyIndex1 ) { struct rtl_mac *mac = &(rtlpriv->mac80211); struct _rtw_hal * pHalData = GET_HAL_DATA(rtlpriv); uint8_t tmpChannel = rtlpriv->phy.current_channel; enum CHANNEL_WIDTH tmpBW= rtlpriv->phy.current_chan_bw; uint8_t tmpnCur40MhzPrimeSC = mac->cur_40_prime_sc; uint8_t tmpnCur80MhzPrimeSC = mac->cur_80_prime_sc; uint8_t tmpCenterFrequencyIndex1 = rtlpriv->phy.current_channel; struct mlme_ext_priv *pmlmeext = &rtlpriv->mlmeextpriv; BOOLEAN bSwChnl = _FALSE, bSetChnlBW = _FALSE; /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d \n",bSwitchChannel,bSetBandWidth); */ /* check is swchnl or setbw */ if(!bSwitchChannel && !bSetBandWidth) { RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, "PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth \n"); return; } /* skip change for channel or bandwidth is the same */ if(bSwitchChannel) { if(rtlpriv->phy.current_channel != ChannelNum) { if (HAL_IsLegalChannel(rtlpriv, ChannelNum)) bSwChnl = _TRUE; else return; } } if(bSetBandWidth) { if(pHalData->bChnlBWInitialzed == _FALSE) { pHalData->bChnlBWInitialzed = _TRUE; bSetChnlBW = _TRUE; } else if((rtlpriv->phy.current_chan_bw != ChnlWidth) || (mac->cur_40_prime_sc != ChnlOffsetOf40MHz) || (mac->cur_80_prime_sc != ChnlOffsetOf80MHz) || (rtlpriv->phy.current_channel != CenterFrequencyIndex1)) { bSetChnlBW = _TRUE; } } if(!bSetChnlBW && !bSwChnl) { /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d \n",bSwChnl,bSetChnlBW); */ return; } if(bSwChnl) { rtlpriv->phy.current_channel = ChannelNum; } if(bSetChnlBW) { rtlpriv->phy.current_chan_bw = ChnlWidth; mac->cur_40_prime_sc = ChnlOffsetOf40MHz; mac->cur_80_prime_sc = ChnlOffsetOf80MHz; } /* Switch workitem or set timer to do switch channel or setbandwidth operation */ if((!rtlpriv->bDriverStopped) && (!rtlpriv->bSurpriseRemoved)) { struct rtl_hal *rtlhal = rtl_hal(rtlpriv); /* DBG_871X("phy_SwChnlAndSetBwMode8812(): bSwChnl %d, bSetChnlBW %d \n", bSwChnl, bSetChnlBW); */ if ((rtlpriv->bDriverStopped) || (rtlpriv->bSurpriseRemoved)) { return; } if (bSwChnl) { rtl8821au_phy_sw_chnl_callback(rtlpriv); bSwChnl = _FALSE; } if (bSetChnlBW) { rtlpriv->cfg->ops->phy_set_bw_mode_callback(rtlpriv); bSetChnlBW = _FALSE; } rtl8821au_dm_clean_txpower_tracking_state(rtlpriv); PHY_SetTxPowerLevel8812(rtlpriv, rtlpriv->phy.current_channel); if ((rtlpriv->phy.need_iqk = false == true)) { if(IS_HARDWARE_TYPE_8812(rtlhal)) rtl8812au_phy_iq_calibrate(rtlpriv, _FALSE); else if(IS_HARDWARE_TYPE_8821(rtlhal)) rtl8821au_phy_iq_calibrate(rtlpriv, _FALSE); rtlpriv->phy.need_iqk = false; } } else { if(bSwChnl) { rtlpriv->phy.current_channel = tmpChannel; } if(bSetChnlBW) { rtlpriv->phy.current_chan_bw = tmpBW; mac->cur_40_prime_sc = tmpnCur40MhzPrimeSC; mac->cur_80_prime_sc = tmpnCur80MhzPrimeSC; } } /* * DBG_871X("Channel %d ChannelBW %d ",pHalData->CurrentChannel, pHalData->CurrentChannelBW); * DBG_871X("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); * DBG_871X("CenterFrequencyIndex1 %d \n",pHalData->CurrentCenterFrequencyIndex1); */ /* * DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d \n",bSwChnl,bSetChnlBW); */ }