bool intelInitContext(struct intel_context *intel, int api, const struct gl_config * mesaVis, __DRIcontext * driContextPriv, void *sharedContextPrivate, struct dd_function_table *functions) { struct gl_context *ctx = &intel->ctx; struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate; __DRIscreen *sPriv = driContextPriv->driScreenPriv; struct intel_screen *intelScreen = sPriv->driverPrivate; int bo_reuse_mode; struct gl_config visual; /* we can't do anything without a connection to the device */ if (intelScreen->bufmgr == NULL) return false; /* Can't rely on invalidate events, fall back to glViewport hack */ if (!driContextPriv->driScreenPriv->dri2.useInvalidate) { intel->saved_viewport = functions->Viewport; functions->Viewport = intel_viewport; } if (mesaVis == NULL) { memset(&visual, 0, sizeof visual); mesaVis = &visual; } if (!_mesa_initialize_context(&intel->ctx, api, mesaVis, shareCtx, functions)) { printf("%s: failed to init mesa context\n", __FUNCTION__); return false; } driContextPriv->driverPrivate = intel; intel->intelScreen = intelScreen; intel->driContext = driContextPriv; intel->driFd = sPriv->fd; intel->gen = intelScreen->gen; const int devID = intelScreen->deviceID; if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID)) intel->gt = 1; else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID)) intel->gt = 2; else intel->gt = 0; if (IS_HASWELL(devID)) { intel->is_haswell = true; } else if (IS_G4X(devID)) { intel->is_g4x = true; } else if (IS_945(devID)) { intel->is_945 = true; } if (intel->gen >= 5) { intel->needs_ff_sync = true; } intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil; intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil; intel->has_hiz = intel->gen >= 6 && !intel->is_haswell; intel->has_llc = intel->intelScreen->hw_has_llc; intel->has_swizzling = intel->intelScreen->hw_has_swizzling; memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported)); driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache, sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915"); if (intel->gen < 4) intel->maxBatchSize = 4096; else intel->maxBatchSize = sizeof(intel->batch.map); intel->bufmgr = intelScreen->bufmgr; bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); switch (bo_reuse_mode) { case DRI_CONF_BO_REUSE_DISABLED: break; case DRI_CONF_BO_REUSE_ALL: intel_bufmgr_gem_enable_reuse(intel->bufmgr); break; } ctx->Const.MinLineWidth = 1.0; ctx->Const.MinLineWidthAA = 1.0; ctx->Const.MaxLineWidth = 5.0; ctx->Const.MaxLineWidthAA = 5.0; ctx->Const.LineWidthGranularity = 0.5; ctx->Const.MinPointSize = 1.0; ctx->Const.MinPointSizeAA = 1.0; ctx->Const.MaxPointSize = 255.0; ctx->Const.MaxPointSizeAA = 3.0; ctx->Const.PointSizeGranularity = 1.0; ctx->Const.MaxSamples = 1.0; if (intel->gen >= 6) ctx->Const.MaxClipPlanes = 8; ctx->Const.StripTextureBorder = GL_TRUE; /* reinitialize the context point state. * It depend on constants in __struct gl_contextRec::Const */ _mesa_init_point(ctx); if (intel->gen >= 4) { ctx->Const.MaxRenderbufferSize = 8192; } else { ctx->Const.MaxRenderbufferSize = 2048; } /* Initialize the software rasterizer and helper modules. * * As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for * software fallbacks (which we have to support on legacy GL to do weird * glDrawPixels(), glBitmap(), and other functions). */ if (intel->gen <= 3 || api != API_OPENGL_CORE) { _swrast_CreateContext(ctx); } _vbo_CreateContext(ctx); if (ctx->swrast_context) { _tnl_CreateContext(ctx); _swsetup_CreateContext(ctx); /* Configure swrast to match hardware characteristics: */ _swrast_allow_pixel_fog(ctx, false); _swrast_allow_vertex_fog(ctx, true); } _mesa_meta_init(ctx); intel->hw_stencil = mesaVis->stencilBits && mesaVis->depthBits == 24; intel->hw_stipple = 1; /* XXX FBO: this doesn't seem to be used anywhere */ switch (mesaVis->depthBits) { case 0: /* what to do in this case? */ case 16: intel->polygon_offset_scale = 1.0; break; case 24: intel->polygon_offset_scale = 2.0; /* req'd to pass glean */ break; default: assert(0); break; } if (intel->gen >= 4) intel->polygon_offset_scale /= 0xffff; intel->RenderIndex = ~0; intelInitExtensions(ctx); INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control); if (INTEL_DEBUG & DEBUG_BUFMGR) dri_bufmgr_set_debug(intel->bufmgr, true); if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && intel->gen < 7) { fprintf(stderr, "shader_time debugging requires gen7 (Ivybridge) or better.\n"); INTEL_DEBUG &= ~DEBUG_SHADER_TIME; } if (INTEL_DEBUG & DEBUG_AUB) drm_intel_bufmgr_gem_set_aub_dump(intel->bufmgr, true); intel_batchbuffer_init(intel); intel_fbo_init(intel); intel->use_texture_tiling = driQueryOptionb(&intel->optionCache, "texture_tiling"); intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z"); if (!driQueryOptionb(&intel->optionCache, "hiz")) { intel->has_hiz = false; /* On gen6, you can only do separate stencil with HIZ. */ if (intel->gen == 6) intel->has_separate_stencil = false; } intel->prim.primitive = ~0; /* Force all software fallbacks */ #ifdef I915 if (driQueryOptionb(&intel->optionCache, "no_rast")) { fprintf(stderr, "disabling 3D rasterization\n"); intel->no_rast = 1; } #endif if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) { fprintf(stderr, "flushing batchbuffer before/after each draw call\n"); intel->always_flush_batch = 1; } if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) { fprintf(stderr, "flushing GPU caches before/after each draw call\n"); intel->always_flush_cache = 1; } return true; }
bool intelInitContext(struct brw_context *brw, int api, unsigned major_version, unsigned minor_version, const struct gl_config * mesaVis, __DRIcontext * driContextPriv, void *sharedContextPrivate, struct dd_function_table *functions, unsigned *dri_ctx_error) { struct gl_context *ctx = &brw->ctx; struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate; __DRIscreen *sPriv = driContextPriv->driScreenPriv; struct intel_screen *intelScreen = sPriv->driverPrivate; int bo_reuse_mode; struct gl_config visual; /* we can't do anything without a connection to the device */ if (intelScreen->bufmgr == NULL) { *dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY; return false; } if (!validate_context_version(intelScreen, api, major_version, minor_version, dri_ctx_error)) return false; /* Can't rely on invalidate events, fall back to glViewport hack */ if (!driContextPriv->driScreenPriv->dri2.useInvalidate) { brw->saved_viewport = functions->Viewport; functions->Viewport = intel_viewport; } if (mesaVis == NULL) { memset(&visual, 0, sizeof visual); mesaVis = &visual; } brw->intelScreen = intelScreen; if (!_mesa_initialize_context(&brw->ctx, api, mesaVis, shareCtx, functions)) { *dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY; printf("%s: failed to init mesa context\n", __FUNCTION__); return false; } driContextPriv->driverPrivate = brw; brw->driContext = driContextPriv; brw->gen = intelScreen->gen; const int devID = intelScreen->deviceID; if (IS_SNB_GT1(devID) || IS_IVB_GT1(devID) || IS_HSW_GT1(devID)) brw->gt = 1; else if (IS_SNB_GT2(devID) || IS_IVB_GT2(devID) || IS_HSW_GT2(devID)) brw->gt = 2; else if (IS_HSW_GT3(devID)) brw->gt = 3; else brw->gt = 0; if (IS_HASWELL(devID)) { brw->is_haswell = true; } else if (IS_BAYTRAIL(devID)) { brw->is_baytrail = true; brw->gt = 1; } else if (IS_G4X(devID)) { brw->is_g4x = true; } brw->has_separate_stencil = brw->intelScreen->hw_has_separate_stencil; brw->must_use_separate_stencil = brw->intelScreen->hw_must_use_separate_stencil; brw->has_hiz = brw->gen >= 6; brw->has_llc = brw->intelScreen->hw_has_llc; brw->has_swizzling = brw->intelScreen->hw_has_swizzling; memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported)); driParseConfigFiles(&brw->optionCache, &intelScreen->optionCache, sPriv->myNum, "i965"); /* Estimate the size of the mappable aperture into the GTT. There's an * ioctl to get the whole GTT size, but not one to get the mappable subset. * It turns out it's basically always 256MB, though some ancient hardware * was smaller. */ uint32_t gtt_size = 256 * 1024 * 1024; /* We don't want to map two objects such that a memcpy between them would * just fault one mapping in and then the other over and over forever. So * we would need to divide the GTT size by 2. Additionally, some GTT is * taken up by things like the framebuffer and the ringbuffer and such, so * be more conservative. */ brw->max_gtt_map_object_size = gtt_size / 4; brw->bufmgr = intelScreen->bufmgr; bo_reuse_mode = driQueryOptioni(&brw->optionCache, "bo_reuse"); switch (bo_reuse_mode) { case DRI_CONF_BO_REUSE_DISABLED: break; case DRI_CONF_BO_REUSE_ALL: intel_bufmgr_gem_enable_reuse(brw->bufmgr); break; } /* Initialize the software rasterizer and helper modules. * * As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for * software fallbacks (which we have to support on legacy GL to do weird * glDrawPixels(), glBitmap(), and other functions). */ if (api != API_OPENGL_CORE && api != API_OPENGLES2) { _swrast_CreateContext(ctx); } _vbo_CreateContext(ctx); if (ctx->swrast_context) { _tnl_CreateContext(ctx); _swsetup_CreateContext(ctx); /* Configure swrast to match hardware characteristics: */ _swrast_allow_pixel_fog(ctx, false); _swrast_allow_vertex_fog(ctx, true); } _mesa_meta_init(ctx); intelInitExtensions(ctx); INTEL_DEBUG = driParseDebugString(getenv("INTEL_DEBUG"), debug_control); if (INTEL_DEBUG & DEBUG_BUFMGR) dri_bufmgr_set_debug(brw->bufmgr, true); if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && brw->gen < 7) { fprintf(stderr, "shader_time debugging requires gen7 (Ivybridge) or better.\n"); INTEL_DEBUG &= ~DEBUG_SHADER_TIME; } if (INTEL_DEBUG & DEBUG_PERF) brw->perf_debug = true; if (INTEL_DEBUG & DEBUG_AUB) drm_intel_bufmgr_gem_set_aub_dump(brw->bufmgr, true); intel_batchbuffer_init(brw); intel_fbo_init(brw); if (!driQueryOptionb(&brw->optionCache, "hiz")) { brw->has_hiz = false; /* On gen6, you can only do separate stencil with HIZ. */ if (brw->gen == 6) brw->has_separate_stencil = false; } if (driQueryOptionb(&brw->optionCache, "always_flush_batch")) { fprintf(stderr, "flushing batchbuffer before/after each draw call\n"); brw->always_flush_batch = 1; } if (driQueryOptionb(&brw->optionCache, "always_flush_cache")) { fprintf(stderr, "flushing GPU caches before/after each draw call\n"); brw->always_flush_cache = 1; } if (driQueryOptionb(&brw->optionCache, "disable_throttling")) { fprintf(stderr, "disabling flush throttling\n"); brw->disable_throttling = 1; } return true; }