/**
* @brief Initializes the SPDIFRX peripheral according to the specified
* parameters in the SPDIFRX_InitStruct.
*
* @note SPDIFRX clock is generated from a specific output of the PLLSPDIFRX or a specific
* output of the PLLI2S or from an alternate function bypassing the PLL I2S.
*
* @param SPDIFRX_InitStruct: pointer to a SPDIFRX_InitTypeDef structure that
* contains the configuration information for the specified SPDIFRX Block peripheral.
* @retval None
*/
void SPDIFRX_Init(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct)
{
uint32_t tmpreg = 0;
/* Check the SPDIFRX parameters */
assert_param(IS_STEREO_MODE(SPDIFRX_InitStruct->SPDIFRX_StereoMode));
assert_param(IS_SPDIFRX_INPUT_SELECT(SPDIFRX_InitStruct->SPDIFRX_InputSelection));
assert_param(IS_SPDIFRX_MAX_RETRIES(SPDIFRX_InitStruct->SPDIFRX_Retries));
assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(SPDIFRX_InitStruct->SPDIFRX_WaitForActivity));
assert_param(IS_SPDIFRX_CHANNEL(SPDIFRX_InitStruct->SPDIFRX_ChannelSelection));
assert_param(IS_SPDIFRX_DATA_FORMAT(SPDIFRX_InitStruct->SPDIFRX_DataFormat));
/* SPDIFRX CR Configuration */
/* Get the SPDIFRX CR value */
tmpreg = SPDIFRX->CR;
/* Clear INSEL, WFA, NBTR, CHSEL, DRFMT and RXSTEO bits */
tmpreg &= CR_CLEAR_MASK;
/* Configure SPDIFRX: Input selection, Maximum allowed re-tries during synchronization phase,
wait for activity, Channel Selection, Data samples format and stereo/mono mode */
/* Set INSEL bits according to SPDIFRX_InputSelection value */
/* Set WFA bit according to SPDIFRX_WaitForActivity value */
/* Set NBTR bit according to SPDIFRX_Retries value */
/* Set CHSEL bit according to SPDIFRX_ChannelSelection value */
/* Set DRFMT bits according to SPDIFRX_DataFormat value */
/* Set RXSTEO bit according to SPDIFRX_StereoMode value */
tmpreg |= (uint32_t)(SPDIFRX_InitStruct->SPDIFRX_InputSelection | SPDIFRX_InitStruct->SPDIFRX_WaitForActivity |
SPDIFRX_InitStruct->SPDIFRX_Retries | SPDIFRX_InitStruct->SPDIFRX_ChannelSelection |
SPDIFRX_InitStruct->SPDIFRX_DataFormat | SPDIFRX_InitStruct->SPDIFRX_StereoMode
);
/* Write to SPDIFRX CR */
SPDIFRX->CR = tmpreg;
}
/**
* @brief Sets the SPDIFRX dtat format according to the specified parameters
* in the SPDIFRX_InitTypeDef.
* @param hspdif: SPDIFRX handle
* @param sDataFormat: SPDIFRX data format
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat)
{
uint32_t tmpreg = 0;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
{
return HAL_ERROR;
}
/* Check the SPDIFRX parameters */
assert_param(IS_STEREO_MODE(sDataFormat.StereoMode));
assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat));
assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask));
assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask));
assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask));
assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask));
/* Reset the old SPDIFRX CR configuration */
tmpreg = hspdif->Instance->CR;
if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) &&
(((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) ||
((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode)))
{
return HAL_ERROR;
}
tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK);
/* Sets the new configuration of the SPDIFRX peripheral */
tmpreg |= ((uint16_t) sDataFormat.StereoMode |
sDataFormat.DataFormat |
sDataFormat.PreambleTypeMask |
sDataFormat.ChannelStatusMask |
sDataFormat.ValidityBitMask |
sDataFormat.ParityErrorMask);
hspdif->Instance->CR = tmpreg;
return HAL_OK;
}
/**
* @brief Initializes the SPDIFRX according to the specified parameters
* in the SPDIFRX_InitTypeDef and create the associated handle.
* @param hspdif: SPDIFRX handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif)
{
uint32_t tmpreg = 0;
/* Check the SPDIFRX handle allocation */
if(hspdif == NULL)
{
return HAL_ERROR;
}
/* Check the SPDIFRX parameters */
assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode));
assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection));
assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries));
assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity));
assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection));
assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat));
assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask));
assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask));
assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask));
assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask));
if(hspdif->State == HAL_SPDIFRX_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hspdif->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_SPDIFRX_MspInit(hspdif);
}
/* SPDIFRX peripheral state is BUSY*/
hspdif->State = HAL_SPDIFRX_STATE_BUSY;
/* Disable SPDIFRX interface (IDLE State) */
__HAL_SPDIFRX_IDLE(hspdif);
/* Reset the old SPDIFRX CR configuration */
tmpreg = hspdif->Instance->CR;
tmpreg &= ~((uint16_t) SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK |
SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK |
SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | SPDIFRX_CR_INSEL);
/* Sets the new configuration of the SPDIFRX peripheral */
tmpreg |= ((uint16_t) hspdif->Init.StereoMode |
hspdif->Init.InputSelection |
hspdif->Init.Retries |
hspdif->Init.WaitForActivity |
hspdif->Init.ChannelSelection |
hspdif->Init.DataFormat |
hspdif->Init.PreambleTypeMask |
hspdif->Init.ChannelStatusMask |
hspdif->Init.ValidityBitMask |
hspdif->Init.ParityErrorMask);
hspdif->Instance->CR = tmpreg;
hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE;
/* SPDIFRX peripheral state is READY*/
hspdif->State = HAL_SPDIFRX_STATE_READY;
return HAL_OK;
}