/**
* ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
* @hw: pointer to hardware structure
* @dcb_config: pointer to ixgbe_dcb_config structure
*
* Configure Tx Data Arbiter and credits for each traffic class.
*/
s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
u16 *refill,
u16 *max,
u8 *bwg_id,
u8 *prio_type)
{
u32 reg;
u8 i;
reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
/* Enable Data Plane Arbiter */
reg &= ~IXGBE_PDPMCS_ARBDIS;
/* Enable DFP and Transmit Recycle Mode */
reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
/* Configure traffic class credits and priority */
for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
reg = refill[i];
reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
if (prio_type[i] == prio_group)
reg |= IXGBE_TDPT2TCCR_GSP;
if (prio_type[i] == prio_link)
reg |= IXGBE_TDPT2TCCR_LSP;
IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
}
/* Enable Tx packet buffer division */
reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
reg |= IXGBE_DTXCTL_ENDBUBD;
IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
return 0;
}
static void ixgbe_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *p)
{
struct ixgbe_adapter *adapter = netdev_priv(netdev);
struct ixgbe_hw *hw = &adapter->hw;
u32 *regs_buff = p;
u8 i;
memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
/* General Registers */
regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
/* NVM Register */
regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
/* Interrupt */
/* don't read EICR because it can clear interrupt causes, instead
* read EICS which is a shadow but doesn't clear EICR */
regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
/* Flow Control */
regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
for (i = 0; i < 8; i++)
regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
for (i = 0; i < 8; i++)
regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
/* Receive DMA */
for (i = 0; i < 64; i++)
regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
for (i = 0; i < 64; i++)
regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
for (i = 0; i < 64; i++)
regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
for (i = 0; i < 64; i++)
regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
for (i = 0; i < 64; i++)
regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
for (i = 0; i < 64; i++)
regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
for (i = 0; i < 16; i++)
regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
for (i = 0; i < 16; i++)
regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
for (i = 0; i < 8; i++)
regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
/* Receive */
regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
for (i = 0; i < 16; i++)
regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
for (i = 0; i < 16; i++)
regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
for (i = 0; i < 8; i++)
regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
for (i = 0; i < 8; i++)
regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
/* Transmit */
for (i = 0; i < 32; i++)
regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
for (i = 0; i < 32; i++)
regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
for (i = 0; i < 32; i++)
regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
for (i = 0; i < 32; i++)
regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
for (i = 0; i < 32; i++)
regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
for (i = 0; i < 32; i++)
regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
for (i = 0; i < 32; i++)
regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
for (i = 0; i < 32; i++)
regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
for (i = 0; i < 16; i++)
regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
for (i = 0; i < 8; i++)
regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
/* Wake Up */
regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT);
regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
for (i = 0; i < 8; i++)
regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
for (i = 0; i < 8; i++)
regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
for (i = 0; i < 8; i++)
regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
for (i = 0; i < 8; i++)
regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
for (i = 0; i < 8; i++)
regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
for (i = 0; i < 8; i++)
regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
/* Statistics */
regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
for (i = 0; i < 8; i++)
regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
for (i = 0; i < 8; i++)
regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
for (i = 0; i < 8; i++)
regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
for (i = 0; i < 8; i++)
regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
for (i = 0; i < 8; i++)
regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
for (i = 0; i < 8; i++)
regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
for (i = 0; i < 16; i++)
regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
for (i = 0; i < 16; i++)
regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
for (i = 0; i < 16; i++)
regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
for (i = 0; i < 16; i++)
regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
/* MAC */
regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
/* Diagnostic */
regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
for (i = 0; i < 8; i++)
regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
for (i = 0; i < 4; i++)
regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
for (i = 0; i < 8; i++)
regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
for (i = 0; i < 4; i++)
regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
for (i = 0; i < 8; i++)
regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
}