IX_STATUS ixParityENAccAqmPEInit (IxParityENAccInternalCallback ixAqmPECallback) { UINT32 aqmVirtualBaseAddr = 0; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixAqmPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the AQM registers */ aqmVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_AQM_BASEADDR, IXP400_PARITYENACC_AQM_MEMMAP_SIZE); if ((UINT32)NULL == aqmVirtualBaseAddr) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for AQM Registers */ ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr = aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEADDRERR_OFFSET; ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueDataErr = aqmVirtualBaseAddr + IXP400_PARITYENACC_AQM_QUEDATAERR_OFFSET; /* Register main module internal callback routine for AQM */ ixParityENAccAqmPEConfig.aqmPECallback = ixAqmPECallback; /* Interrupt Service Routine Info for AQM for debug purpose */ ixParityENAccAqmPEConfig.aqmIsrInfo.aqmInterruptId = IRQ_IXP400_INTC_PARITYENACC_AQM; ixParityENAccAqmPEConfig.aqmIsrInfo.aqmIsr = ixParityENAccAqmPEIsr; /* Disable parity error detection */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_ENABLE | IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_FLAG); /* Install AQM Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_AQM, (IxOsalVoidFnVoidPtr) ixParityENAccAqmPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(aqmVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccAqmPEInit() function */
IX_STATUS ixParityENAccAqmPEParityInterruptClear (void) { /* Clear off parity error details */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccAqmPEConfig.aqmPERegisters.aqmQueAddErr, IXP400_PARITYENACC_AQM_QUEADDRERR_PERR_FLAG); /* Disable the interrupt from triggering further */ return ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_AQM_PARITY_INTERRUPT); } /* end of ixParityENAccAqmPEParityInterruptClear() function */
IX_STATUS ixParityENAccEbcPEInit (IxParityENAccInternalCallback ixEbcPECallback) { UINT32 ebcVirtualBaseAddr = 0; IxParityENAccChipSelectId csId = IXP400_PARITYENACC_PE_EBC_CHIPSEL0; register IxParityENAccEbcPERegisters *ebcPERegisters = &ixParityENAccEbcPEConfig.ebcPERegisters; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixEbcPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the EBC registers */ if ((UINT32)NULL == (ebcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_EBC_BASEADDR, IXP400_PARITYENACC_EBC_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for EBC Registers */ ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL0] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS0_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL1] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS1_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL2] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS2_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL3] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS3_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL4] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS4_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL5] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS5_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL6] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS6_OFFSET; ebcPERegisters->expTimingCs[IXP400_PARITYENACC_PE_EBC_CHIPSEL7] = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_TIMING_CS7_OFFSET; ebcPERegisters->expMstControl = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_MST_CONTROL_OFFSET; ebcPERegisters->expParityStatus = ebcVirtualBaseAddr + IXP400_PARITYENACC_EBC_PARITY_STATUS_OFFSET; /* Register main module internal callback routine */ ixParityENAccEbcPEConfig.ebcPECallback = ixEbcPECallback; /* Interrupt Service Routine Info for debug purpose */ ixParityENAccEbcPEConfig.ebcIsrInfo.ebcInterruptId = IRQ_IXP400_INTC_PARITYENACC_EBC; ixParityENAccEbcPEConfig.ebcIsrInfo.ebcIsr = ixParityENAccEbcPEIsr; /* Disable parity error detection on both Inbound & Outbound interfaces */ for (; csId < IXP400_PARITYENACC_PE_EBC_CHIPSEL_MAX; csId++) { IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expTimingCs[csId], IXP400_PARITYENACC_EBC_TIMING_CSX_PAR_EN); } /* end of for */ IXP400_PARITYENACC_REG_BIT_CLEAR(ebcPERegisters->expMstControl, IXP400_PARITYENACC_EBC_MST_CONTROL_INPAR_EN); /* Install EBC Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_EBC, (IxOsalVoidFnVoidPtr) ixParityENAccEbcPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_EBC_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(ebcVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccEbcPEInit() function */
IX_STATUS ixParityENAccMcuPEInit (IxParityENAccInternalCallback ixMcuPECallback) { UINT32 virtualBaseAddr = 0; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixMcuPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the MCU registers */ if ((UINT32)NULL == (virtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_MCU_BASEADDR, IXP400_PARITYENACC_MCU_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ /* Virtual Addresses assignment for MCU Registers */ ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECCR_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog0 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG0_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuElog1 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ELOG1_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar0 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR0_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuEcar1 = virtualBaseAddr + IXP400_PARITYENACC_MCU_ECAR1_OFFSET; ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr = virtualBaseAddr + IXP400_PARITYENACC_MCU_MCISR_OFFSET; /* Register main module internal callback routine */ ixParityENAccMcuPEConfig.mcuPECallback = ixMcuPECallback; /* Interrupt Service Routine Info for debug purpose only */ ixParityENAccMcuPEConfig.mcuIsrInfo.mcuInterruptId = IRQ_IXP400_INTC_PARITYENACC_MCU; ixParityENAccMcuPEConfig.mcuIsrInfo.mcuIsr = ixParityENAccMcuPEIsr; /* * Disable parity error detection for both single and multi-bit ECC * and correction of single bit parity using ECC */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccMcuPEConfig.mcuPERegisters.mcuEccr, IXP400_PARITYENACC_MCU_SBIT_CORRECT_MASK | IXP400_PARITYENACC_MCU_MBIT_REPORT_MASK | IXP400_PARITYENACC_MCU_SBIT_REPORT_MASK); /* Clear off the pending interrupts, if any */ IXP400_PARITYENACC_REG_BIT_SET( ixParityENAccMcuPEConfig.mcuPERegisters.mcuMcisr, IXP400_PARITYENACC_MCU_ERROR0_MASK | IXP400_PARITYENACC_MCU_ERROR1_MASK | IXP400_PARITYENACC_MCU_ERRORN_MASK); /* Install MCU Interrupt Service Routine after disabling the interrupt */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_MCU, (IxOsalVoidFnVoidPtr) ixParityENAccMcuPEIsr, (void *) NULL)) || (IX_SUCCESS != ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_MCU_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP (virtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccMcuPEInit() function */
IX_STATUS ixParityENAccPbcPEInit(IxParityENAccInternalCallback ixPbcPECallback) { UINT32 pbcVirtualBaseAddr = 0; register IxParityENAccPbcPERegisters *pbcPERegisters = &ixParityENAccPbcPEConfig.pbcPERegisters; /* Verify parameters */ if ((IxParityENAccInternalCallback)NULL == ixPbcPECallback) { return IX_FAIL; } /* end of if */ /* Memory mapping of the PBC registers */ if ((UINT32)NULL == (pbcVirtualBaseAddr = (UINT32) IX_OSAL_MEM_MAP ( IXP400_PARITYENACC_PBC_PCICSR_BASEADDR, IXP400_PARITYENACC_PBC_PCICSR_MEMMAP_SIZE))) { return IX_FAIL; } /* end of if */ ixPbcVirtualBaseAddr = pbcVirtualBaseAddr; /* Virtual Addresses assignment for PBC Control and Status Registers */ pbcPERegisters->pciCrpAdCbe = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_AD_CBE_OFFSET; pbcPERegisters->pciCrpWdata = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_WDATA_OFFSET; pbcPERegisters->pciCrpRdata = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CRP_RDATA_OFFSET; pbcPERegisters->pciCsr = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_CSR_OFFSET; pbcPERegisters->pciIsr = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_ISR_OFFSET; pbcPERegisters->pciInten = pbcVirtualBaseAddr + IXP400_PARITYENACC_PBC_INTEN_OFFSET; /* Register main module internal callback routine */ ixParityENAccPbcPEConfig.pbcPECallback = ixPbcPECallback; /* Interrupt Service Routine Info for debug purpose */ ixParityENAccPbcPEConfig.pbcIsrInfo.pbcInterruptId = IRQ_IXP400_INTC_PARITYENACC_PBC; ixParityENAccPbcPEConfig.pbcIsrInfo.pbcIsr = ixParityENAccPbcPEIsr; /* Disable parity error detection */ /* Write '1' to clear-off the PPE bit */ IXP400_PARITYENACC_REG_BIT_SET( pbcPERegisters->pciIsr, IXP400_PARITYENACC_PBC_ISR_PPE); IXP400_PARITYENACC_REG_BIT_CLEAR( pbcPERegisters->pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); /* Install PBC Interrupt Service Routine */ { INT32 lockKey = ixOsalIrqLock(); if ((IX_SUCCESS != ixOsalIrqBind ((UINT32) IRQ_IXP400_INTC_PARITYENACC_PBC, (IxOsalVoidFnVoidPtr) ixParityENAccPbcPEIsr, (void *) NULL)) || (IX_FAIL == ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT))) { ixOsalIrqUnlock(lockKey); IX_OSAL_MEM_UNMAP(pbcVirtualBaseAddr); return IX_FAIL; } /* end of if */ ixOsalIrqUnlock(lockKey); } return IX_SUCCESS; } /* end of ixParityENAccPbcPEInit() function */
IX_STATUS ixParityENAccPbcPEDetectionConfigure(IxParityENAccPbcPEConfigOption ixPbcPDCfg) { UINT32 pbcPDCfgStatus = 0; UINT32 pbcTmpPDCfgStatus = 0; int loopIdx = 0; /* Read the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcPDCfgStatus); /* * Set/Clear the PER bit of SRCR register & * Enable/Disable Parity Error Notification */ if (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) { /* Set the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_SET(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Enable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_SET( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* else of if */ else { /* Clear the PER bit of SRCR register */ IXP400_PARITYENACC_VAL_BIT_CLEAR(pbcPDCfgStatus, IXP400_PARITYENACC_PBC_PCICFG_SRCR_PER); /* Disable the PCI Parity Error Interrupt Notification */ IXP400_PARITYENACC_REG_BIT_CLEAR( ixParityENAccPbcPEConfig.pbcPERegisters.pciInten, IXP400_PARITYENACC_PBC_INTEN_PPE); } /* end of if */ /* Write back the PCI Controller PCI Config SRCR register */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_WRITE); IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpWdata, pbcPDCfgStatus); loopIdx = 10; while (loopIdx--) { /* Verify that the configuration is successful or not */ IXP400_PARITYENACC_REG_WRITE( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpAdCbe, IXP400_PARITYENACC_PBC_PCICSR_SRCR_READ); IXP400_PARITYENACC_REG_READ( ixParityENAccPbcPEConfig.pbcPERegisters.pciCrpRdata, &pbcTmpPDCfgStatus); } if (TRUE == IXP400_PARITYENACC_VAL_BIT_CHECK(pbcPDCfgStatus, pbcTmpPDCfgStatus)) { /* Enable/Disable the corresponding interrupt at Interrupt Controller */ return (IXP400_PARITYENACC_PE_ENABLE == ixPbcPDCfg) ? ixParityENAccIcInterruptEnable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT) : ixParityENAccIcInterruptDisable( IXP400_PARITYENACC_INTC_PBC_PARITY_INTERRUPT); } else { return IX_FAIL; } /* end of if */ } /* end of ixParityENAccPbcPEDetectionConfigure() function */